pef22504 Infineon Technologies Corporation, pef22504 Datasheet - Page 73

• Manufacturer Part Number: pef22504
• Description: Quad E1/t1/j1 Line Interface Component For Long- And Short-haul Applications Pef 22504 E, Pef 22504 Ht, Version 2.1
• Manufacturer: Infineon Technologies Corporation

Figure 15
Table 7
Field
VFR
RDO
CRC
RAB
SA1
SA0
C/R
TA
Table 8
Control Bits
(MSB LSB)
01
00
10
11
Table 9
Address
´0000
´0001
´0002
3.5.2.2
The Serial Peripheral Interface (SPI) is selected if IM(1:0) is strapped to ´10
The SPI interface of the QuadLIU
Data Sheet
H
H
H
´
´
´
Bit
7
6
5
4
3
2
1
0
Read Status Byte (RSTA) byte of the SCI Acknowledge (ACK)
Read Status Byte (RSTA) Byte of the SCI Acknowledge (ACK)
Definition of Control Bits in Commands (CMD)
SCI Configuration Register Content
SPI Interface
Bit 7
(MSB)
PP
1
0
Command type
Read QuadLIU
Write QuadLIU
Write SCI configuration register
Read SCI configuration register
7 (MSB)
VFR
Valid Frame. Indicates whether a valid frame has received.
´0´: Received frame is invalid.
´1´: Received frame is valid.
Reserved
CRC compare check. Indicates whether a CRC check is failed or not.
´0´: CRC error check failed on the received frame.
´1´: Received frame is free of CRC errors.
Received message aborted. CMD message abortion is declared. The receive message
was aborted by the HOST. A sequence of 7 consecutive ´1´ was detected before closing
the flag. Note that ACK message and therefore RAB will not be send before destination
address was received.
´0´: Data reception is in progress.
´0´: Data reception has been aborted.
Reserved
Reserved
Reserved
Reserved
Description
Bit6
CLK_POL CLK_GAT ACK_EN
Destination Address
Group Address
RDO
TM
TM
TM
register1
registers
is always a slave.
Bit 5
CRC
RAB
Bit 4
73
SA1
Bit 3
INT_EN
SA0
Bit 2
CRC_EN
H
´.
C/R
QLIU_SCI_RSTA
0 (LSB)
Functional Description
Bit 1
ARB
1 (=C/R)
1 (=C/R)
TA
Rev. 1.3, 2006-01-25
QuadLIU
PEF 22504
Bit 0
DUP
0 (=MS)
0 (=MS)
TM