pef22504 Infineon Technologies Corporation, pef22504 Datasheet - Page 209

• Manufacturer Part Number: pef22504
• Description: Quad E1/t1/j1 Line Interface Component For Long- And Short-haul Applications Pef 22504 E, Pef 22504 Ht, Version 2.1
• Manufacturer: Infineon Technologies Corporation

Interrupt Status Register 3
All bits are reset when ISR3 is read. If bit GCR.VIS is set, interrupt statuses in ISR3 are flagged although they are
masked by register IMR3. However, these masked interrupt statuses neither generate a signal on INT, nor are
visible in register GIS, see
ISR3
Interrupt Status Register 3
Field
SEC
LLBSC
RSN
RSP
Data Sheet
Bits
6
3
1
0
Chapter
Type
rsc
rsc
rsc
rcs
3.5.3.
Description
Second Timer
The internal one-second timer has expired. The timer is derived from
clock RCLK or external pin SEC/FSC.
Line Loop-Back Status Change, T1/J1 only
In E1 mode this bit is not valid and ISR1.LLBSC is used instead.
Depending on bit LCR1.EPRM the source of this interrupt status
changed:
•
•
Receive Slip Negative
The frequency of the receive route clock is greater than the frequency of
the receive system interface working clock based on 2.048 MHz. A frame
is skipped. It is set during alarm simulation. See
Receive Slip Positive
The frequency of the receive route clock is less than the frequency of the
receive system interface working clock based on 2.048 MHz. A frame is
repeated. It is set during alarm simulation. See
LCR1.EPRM = 0: This bit is set, if the LLB activate signal or the LLB
deactivate signal, respectively, is detected over a period of 25 ms with
a bit error rate less than 10
detection status is left, i.e., if the bit error rate exceeds 10
detection status can be read from the LSR2.LLBAD / LSR2.LLBDD in
E1 or LSR1.LLBAD / LSR1.LLBDD in T1/J1 mode, respectively.
PRBS Status Change LCR1.EPRM = ´1´: With any change of state of
the PRBS synchronizer this bit is set. The current status of the PRBS
synchronizer is indicated in LSR2.LLBAD (E1) or LSR1.LLBAD
(T1/J1).
Offset
xx6B
209
H
Register DescriptionInterrupt Status Register 3
-2
. The LLBSC bit is also set, if the current
Chapter
Chapter
Rev. 1.3, 2006-01-25
3.7.9.
3.7.9.
QuadLIU
-2
PEF 22504
Reset Value
. The actual
00
TM
H