pef22504 Infineon Technologies Corporation, pef22504 Datasheet - Page 66

• Manufacturer Part Number: pef22504
• Description: Quad E1/t1/j1 Line Interface Component For Long- And Short-haul Applications Pef 22504 E, Pef 22504 Ht, Version 2.1
• Manufacturer: Infineon Technologies Corporation

Figure 8
3.2
The QuadLIU
external microprocessor or micro controller, using either the asynchronous interface, SPI bus or SCI bus.
The register address range is 10 bit wide.
3.3
The main interfaces are
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As well as several control lines for reset, mode and clocking purpose.
The main internal functional blocks are
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Data Sheet
Receive and transmit line interface
Asynchronous Microprocessor interface with two modes: Intel or Motorola
SPI Bus interface
SCI Bus interface
Framer interface
Boundary scan interface
Analog line receiver with equalizer network and clock/data recovery
Analog line driver with programmable pulse shaper and line build out
Master clock generation unit
Dual elastic buffers for receive and transmit direction, controlled by the appropriate jitter attenuators
Receive line decoding, alarm detection and PRBS monitoring
Transmit line encoding, alarm and PRBS generation
Receive jitter attenuator
Transmit jitter attenuator
Available test loops: Local loop, remote loop and payload loop
Boundary scan control
V
must always be guaranteed,
also during power on and
power down sequences.
Dual Voltage Supply
Software
Functional Overview
DD
TM
, V
device contains analog and digital function blocks that are configured and controlled by an
DDP
, V
DDX
, V
DDR
> V
1.8 V
DDC
3.3 V
66
V
V
V
V
V
V
V
V
V
V
DD
DDX
DDR
DDP
DDC
DDC
SS
SSP
SSX
SSR
QuadLIU
VSEL
Functional Description
Rev. 1.3, 2006-01-25
QLIU_F0249
QuadLIU
PEF 22504
TM