pef22504 Infineon Technologies Corporation, pef22504 Datasheet - Page 207

• Manufacturer Part Number: pef22504
• Description: Quad E1/t1/j1 Line Interface Component For Long- And Short-haul Applications Pef 22504 E, Pef 22504 Ht, Version 2.1
• Manufacturer: Infineon Technologies Corporation

Interrupt Status Register 1
All bits are reset when ISR1 is read. If bit GCR.VIS is set, interrupt statuses in ISR1 are flagged although they are
masked by register IMR1. However, these masked interrupt statuses neither generate a signal on INT, nor are
visible in register GIS, see
ISR1
Interrupt Status Register 1
Field
LLBSC
XLSC
Data Sheet
Bits
7
1
Chapter
Type
rsc
rsc
3.5.3.
Description
Line Loop-Back Status Change, E1 only
In T1/J1 mode this bit is not valid and ISR3.LLBSC is used instead.
Depending on bit LCR1.EPRM the source of this interrupt status
changed:
•
•
Transmit Line Status Change
XLSC is set with the rising edge of the bit LSR1.XLO or with any change
of bit LSR1.XLS.
The actual status of the transmit line monitor can be read from the
LSR1.XLS and LSR1.XLO.
LCR1.EPRM = 0: This bit is set, if the LLB activate signal or the LLB
deactivate signal, respectively, is detected over a period of 25 ms with
a bit error rate less than 10
detection status is left, i.e., if the bit error rate exceeds 10
detection status can be read from the LSR2.LLBAD / LSR2.LLBDD in
E1 or LSR1.LLBAD / LSR1.LLBDD in T1/J1 mode, respectively.
PRBS Status Change LCR1.EPRM = ´1´: With any change of state of
the PRBS synchronizer this bit is set. The current status of the PRBS
synchronizer is indicated in LSR2.LLBAD (E1) or LSR1.LLBAD
(T1/J1).
Offset
xx69
207
H
Register DescriptionInterrupt Status Register 1
-2
. The LLBSC bit is also set, if the current
Rev. 1.3, 2006-01-25
QuadLIU
-2
PEF 22504
Reset Value
. The actual
00
TM
H