pef22504 Infineon Technologies Corporation, pef22504 Datasheet - Page 75

• Manufacturer Part Number: pef22504
• Description: Quad E1/t1/j1 Line Interface Component For Long- And Short-haul Applications Pef 22504 E, Pef 22504 Ht, Version 2.1
• Manufacturer: Infineon Technologies Corporation

Figure 18
Each interrupt indication bit of the registers ISR can be selectively masked by setting the corresponding bit in the
corresponding mask registers IMR. If the interrupt status bits are masked they neither generate an interrupt at INT
nor are they visible in ISR. All reserved bits in the mask registers IMR must not be written with the value ´0´.
GIS, the non-maskable “Global” Interrupt Status Register per channel, serves as pointer to pending interrupts
sourced by registers ISR(1:4), ISR6 and ISR7.
The non-maskable Channel Interrupt Status Register CIS serves as channel pointer to pending interrupts sourced
by registers GIS.
After the QuadLIU
read the register CIS to identify the requesting interrupt source channel. Then it should read the Global Interrupt
Status register GIS to identify the requesting interrupt source register ISR of that channel.
After reading the assigned interrupt status registers ISR(1:4), ISR6 and ISR7, the pointer bit in register GIS is
cleared or updated if another interrupt requires service. After all bits ISR(7:0) of a register GIS are cleared, the
assigned bit in register CIS is cleared. After all bits in register CIS are cleared the INT pin will be deactivated.
If all pending interrupts are acknowledged by reading (GIS is reset), pin INT goes inactive.
Updating of interrupt status registers ISR(1:4), ISR6 and ISR7 and GIS is only prohibited during read access.
Data Sheet
INT
Interrupt Status Registers
TM
has requested an interrupt by activating its INT pin, the external micro controller should first
PLLLC
Channel
Interrupt Status
Register CIS ,
global
GIS4
GIS3
GIS2
GIS1
PLLL
PLL
VISPLL
GIS2
PLLLS not visible
GIMR
IPC
1 to 4
„Global“
Interrupt Status
Register GIS
(per channel)
ISR1
ISR2
ISR3
ISR4
ISR6
ISR7
ISR1
ISR3
ISR4
ISR6
ISR7
R2
75
VIS
ISR4
ISR2
ISR6
GCR
IMR4
IMR2
IMR6
Status Registers and Masking
(shown for one channel)
different Status bits
...
...
...
channel
channel
channel
...
1 to 4
ISR3
ISR1
ISR7
IMR3
IMR1
IMR7
Functional Description
...
...
...
Rev. 1.3, 2006-01-25
QLIU_ISR_2
QuadLIU
PEF 22504
TM