pef22504 Infineon Technologies Corporation, pef22504 Datasheet - Page 22

• Manufacturer Part Number: pef22504
• Description: Quad E1/t1/j1 Line Interface Component For Long- And Short-haul Applications Pef 22504 E, Pef 22504 Ht, Version 2.1
• Manufacturer: Infineon Technologies Corporation

Table 1
Pin No.
H11
H14
H13
L9
J14
Data Sheet
I/O Signals (cont’d)for P/PG-LBGA-160-1
Name
D2
SCI_CLK
SCLK
D1
SCI_RXD
SDI
D0
SCI_TXD
SDO
ALE
RD
DS
Pin Type Buffer
IO
I
I
IO
I
I
IO
I
I
I
I
I
Type
PU
–
–
PU
PU
PU
PU
PP or oD SCI Bus Serial Data Out
PU
PU
PU
PU
22
Function
Data Bus Line 2
SCI Bus Clock
Only used if SCI interface mode is selected by IM(1:0) =
´11b´.
SPI Bus Clock
Only used if SPI interface mode is selected by IM(1:0) =
´10b´.
Data Bus Line 1
SCI Bus Serial Data In
Only used if SCI interface mode is selected by IM(1:0) =
´11b´.
SPI Serial Data In
Only used if SPI interface mode is selected by IM(1:0) =
´10b´.
Data Bus Line 0
Only used if SCI interface mode is selected by IM(1:0) =
´11b´.
SPI Bus Serial Data Out
Only used if SPI interface mode is selected by IM(1:0) =
´10b´.
Address Latch Enable
A high on this line indicates an address on an external
multiplexed address/data bus. The address information
provided on lines A(10:0) is internally latched with the
falling edge of ALE. This function allows the QuadLIU
to be connected to a multiplexed address/data bus
without the need for external latches. In this case, pins
A(7:0) must be connected to the data bus pins
externally. In case of demultiplexed mode this pin can
be connected directly to VDD or can be left open.
Read Enable
Intel bus mode.
This signal indicates a read operation. When the
QuadLIU
the bus drivers to output data from an internal register
addressed by A(10:0) to the Data Bus.
Data Strobe
Motorola bus mode.
This pin serves as input to control read/write operations.
TM
is selected via CS, the RD signal enables
Rev. 1.3, 2006-01-25
Pin Descriptions
QuadLIU
PEF 22504
TM
TM