pef22504 Infineon Technologies Corporation, pef22504 Datasheet - Page 99

• Manufacturer Part Number: pef22504
• Description: Quad E1/t1/j1 Line Interface Component For Long- And Short-haul Applications Pef 22504 E, Pef 22504 Ht, Version 2.1
• Manufacturer: Infineon Technologies Corporation

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Note that these wander configuration is reset by a receive reset (CMDR.RRES = ´1´)
Using this programming and 2 Hz for the corner frequency of the DCO-R, the output wander is given by curve 2.
3.7.9
For jitter attenuation the received data is written into the receive elastic buffer with the recovered clock sourced by
the clock & data recovery and are read out with the de-jittered clock sourced by DCO-R, see
If the receive elastic buffer is read out directly with the recovered receive clock, no jitter attenuation is performed.
If the receive elastic buffer is read out with the receive framer clock FCLKR of the framer interface (FCLKR is
input), the receive elastic buffer performs a clock adoption from the recovered receive clock to FCLKR.
The receive elastic buffer can buffer two data streams so that dual rail mode is possible at the receive framer
interface (RDOP/RDON). In case of single rail mode on the receive framer interface, the bipolar violation signal
BPV is buffered in the same way as the single rail signal and is supported at multi function pin RDON.
The size of the elastic buffer can be configured independently for the receive and transmit direction. Programming
of the receive buffer size is done by DIC1.RBS(1:0), of the transmit buffer size by DIC1.XBS(1:0) see
Table 26
DIC1.RBS(1:0) (DIC1.XBS(1:0)) Mode
00
01
10
11
The functions are:
•
•
•
In “one frame” or short buffer mode the delay through the receive buffer is reduced to an average delay of 128 or
46 bits. In bypass mode the time slot assigner is disabled. Slips are performed in all buffer modes except the
bypass mode. After a slip is detected the read pointer is adjusted to one half of the current buffer size.
Figure 35
pointer (W) and the read pointer (R) of the memory are nearly coincident, i.e. the read pointer is within the slip
limits (S +, S –). If a slip condition is detected, a negative slip (one frame or one half of the current buffer size is
skipped) or a positive slip (one frame or one half of the current buffer size is read out twice) is performed at the
system interface, depending on the difference between RCLK and the current working clock of the receive
Data Sheet
Write ´00
Write ´B1
Write ´32
Write ´AA
Write ´B2
Write ´33
Write ´00
Write ´B3
Clock adoption between framer receive clock (FCLKR input) and internally generated route clock (recovered
line clock), see
Compensation of input wander and jitter.
Reporting and controlling of slips
gives an idea of operation of the dual receive elastic buffer: A slip condition is detected when the write
H
H
H
H
Dual Receive Elastic Buffer
Receive (Transmit) Elastic Buffer Modes
H
H
H
H
´ into REGFD
´ into REGFP
´ into REGFP
´ into REGFD
´ into REGFP
´ into REGFP
´ into REGFP
´ into REGFD
10
01
11 (short buffer
mode)
00
Chapter
3.7.8.
E1
T1/J1
E1
T1/J1
E1
T1/J1
E1
T1/J1
Frame buffer
size (bits)
512
396
256
193
96
Bypass of the receive (transmit) elastic buffer
Bypass of the receive (transmit) elastic buffer
99
Maximum of
wander (UI =
648 ns)
190
140
100
74
38
Average delay
after performing
a slip
256
193
128
96
48
Functional Description
Rev. 1.3, 2006-01-25
Figure
Slip
Performance
Yes
No
QuadLIU
PEF 22504
22.
Table
26:
TM