pef22504 Infineon Technologies Corporation, pef22504 Datasheet - Page 54

• Manufacturer Part Number: pef22504
• Description: Quad E1/t1/j1 Line Interface Component For Long- And Short-haul Applications Pef 22504 E, Pef 22504 Ht, Version 2.1
• Manufacturer: Infineon Technologies Corporation

Table 2
Pin No.
31
System Interface Transmit
2
3
18
19
Data Sheet
Name
SCLKR4
XDI1
SCLKX1
XDI2
SCLKX2
I/O Signals for P-TQFP-144-8 (cont’d)
Pin Type
I/O
I
I
I
I
Buffer
Type
PU
–
PU
–
PU
Function
System Clock Receive, port 4
Working clock for the receive system interface with a
frequency of 16.384/8.192/4.096/2.048 MHz in E1 mode and
16.384/8.192/4.096/2.048 MHz (SIC2.SSC2 = 0
12.352/6.176/3.088/1.544 MHz (SIC2.SSC2 = 1
mode. If the receive elastic store is bypassed, the clock
supplied on this pin is ignored, because RCLK is used to
clock the receive system interface.
If SCLKR4 is configured to be an output, the internal working
clock of the receive system interface sourced by DCO-R or
RCLK is output.
Transmit Data In, port 1
Transmit data received from the system highway. Latching of
data is done with rising or falling transitions of SCLKX1
according to bit SIC3.RESX.
The delay between the beginning of time slot 0 and the initial
edge of SCLKX1 (after SYPX goes active) is determined by
the registers XC(1:0).
In higher (more than 1.544/2.048 Mbit/s) data rates sampling
of data is defined by bits SIC2.SICS(2:0).
System Clock Transmit, port 1
Working clock for the transmit system interface with a
frequency of 16.384/8.192/4.096/2.048 in E1 mode and
16.384/8.192/4.096/2.048 MHz (SIC2.SSC2 = 0
12.352/6.176/3.088/1.544 MHz (SIC2.SSC2 = 1
mode.
Transmit Data In, port 2
Transmit data received from the system highway. Latching of
data is done with rising or falling transitions of SCLKX2
according to bit SIC3.RESX.
The delay between the beginning of time slot 0 and the initial
edge of SCLKX2 (after SYPX goes active) is determined by
the registers XC(1:0).
In higher (more than 1.544/2.048 Mbit/s) data rates sampling
of data is defined by bits SIC2.SICS(2:0).
System Clock Transmit, port 2
Working clock for the transmit system interface with a
frequency of 16.384/8.192/4.096/2.048 in E1 mode and
16.384/8.192/4.096/2.048 MHz (SIC2.SSC2 = 0
12.352/6.176/3.088/1.544 MHz (SIC2.SSC2 = 1
mode.
54
Rev. 1.3, 2006-01-25
Pin Descriptions
QuadLIU
PEF 22504
B
B
B
B
B
B
) or
) in T1/J1
) or
) in T1/J1
) or
) in T1/J1
TM