pef22504 Infineon Technologies Corporation, pef22504 Datasheet - Page 53

• Manufacturer Part Number: pef22504
• Description: Quad E1/t1/j1 Line Interface Component For Long- And Short-haul Applications Pef 22504 E, Pef 22504 Ht, Version 2.1
• Manufacturer: Infineon Technologies Corporation

Table 2
Pin No.
13
27
26
30
Data Sheet
Name
SCLKR2
RDO3
SCLKR3
RDO4
I/O Signals for P-TQFP-144-8 (cont’d)
Pin Type
I/O
O
I/O
O
Buffer
Type
PU
–
PU
–
Function
System Clock Receive, port 2
Working clock for the receive system interface with a
frequency of 16.384/8.192/4.096/2.048 MHz in E1 mode and
16.384/8.192/4.096/2.048 MHz (SIC2.SSC2 = 0
12.352/6.176/3.088/1.544 MHz (SIC2.SSC2 = 1
mode. If the receive elastic store is bypassed, the clock
supplied on this pin is ignored, because RCLK is used to
clock the receive system interface.
If SCLKR2 is configured to be an output, the internal working
clock of the receive system interface sourced by DCO-R or
RCLK is output.
Receive Data Out, port 3
Received data that is sent to the system highway. Clocking
of data is done with the rising or falling edge (SIC3.RESR) of
SCLKR3, if the receive elastic store is bypassed. The delay
between the beginning of time slot 0 and the initial edge of
SCLKR3 (after SYPR goes active) is determined by the
values of registers RC1 and RC0.
If received data is shifted out with higher (more than
2.048/1.544 Mbit/s) data rates, the active channel phase is
defined by bits SIC2.SICS(2:0). During inactive channel
phases RDO3 is cleared (driven to low level, not tristate).
System Clock Receive, port 3
Working clock for the receive system interface with a
frequency of 16.384/8.192/4.096/2.048 MHz in E1 mode and
16.384/8.192/4.096/2.048 MHz (SIC2.SSC2 = 0
12.352/6.176/3.088/1.544 MHz (SIC2.SSC2 = 1
mode. If the receive elastic store is bypassed, the clock
supplied on this pin is ignored, because RCLK is used to
clock the receive system interface.
If SCLKR3 is configured to be an output, the internal working
clock of the receive system interface sourced by DCO-R or
RCLK is output.
Receive Data Out, port 4
Received data that is sent to the system highway. Clocking
of data is done with the rising or falling edge (SIC3.RESR) of
SCLKR4, if the receive elastic store is bypassed. The delay
between the beginning of time slot 0 and the initial edge of
SCLKR4 (after SYPR goes active) is determined by the
values of registers RC1 and RC0.
If received data is shifted out with higher (more than
2.048/1.544 Mbit/s) data rates, the active channel phase is
defined by bits SIC2.SICS(2:0). During inactive channel
phases RDO4 is cleared (driven to low level, not tristate).
53
Rev. 1.3, 2006-01-25
Pin Descriptions
QuadLIU
PEF 22504
B
B
B
B
) or
) in T1/J1
) or
) in T1/J1
TM