pef22504 Infineon Technologies Corporation, pef22504 Datasheet - Page 153

• Manufacturer Part Number: pef22504
• Description: Quad E1/t1/j1 Line Interface Component For Long- And Short-haul Applications Pef 22504 E, Pef 22504 Ht, Version 2.1
• Manufacturer: Infineon Technologies Corporation

Clock Mode Register 6
CMR6
Clock Mode Register 6
Field
DCOCOMPN
SRESR
SRESX
STF
Data Sheet
Bits
7
6
5
4:2
Type
rw
rw
rw
rw
Description
Compatibility Programming of DCO-R/DCO-X Disable
Only applicable if CMR2.ECFAR/ECFAX is set. See
Table
0
1
Soft Reset of DCO-R
By setting this bit a soft reset of the DCO-R will be performed: The initial
phase error is set to zero and the loop filter is cleared. To enable the
DCO-R lock functionality, this bit must be cleared subsequently. See
Chapter
0
1
Soft Reset of DCO-X
By setting this bit a soft reset of the DCO-X will be performed: The initial
phase error is set to zero and the loop filter is cleared. To enable the
DCO-X lock functionality, this bit must be cleared subsequently. See
Chapter
0
1
Transmit Clock (TCLK) Frequency Selection
See
000
001
010
011
100
101
110
111
B
B
B
B
B
B
B
B
B
B
B
B
B
B
Chapter
registers CMR3.CFAR (3:0) /CFAX(3:0), compatible to the
QuadLIU. Register bits CMR5.IAX(4:0)/CMR4.IAR(4:0) are not
valid.
DCO-R/DCO-X is done with registers CMR3.CFAR
(3:0)/CFAX(3:0) and CMR4.IAR(4:0)/CMR5.IAX(4:0) in the range
0.2 ... 20 Hz.
programming of corner frequencies of DCO-R/DCO-X is done with
programming of corner frequencies and attenuation factors of
DCO-R enabled (normal lock functionality).
soft reset of DCO-R, no lock functionality.
DCO-X enabled (normal lock functionality).
soft reset of DCO-X, no lock functionality.
2.048 MHz.
8.192 MHz.
4.096 MHz.
16.384 MHz.
32.768 MHz.
reserved.
reserved.
reserved.
23.
3.7.8.
3.7.8.
Offset
xx43
3.9.2. Note that frequencies are not in ascent ordering.
153
H
Register DescriptionClock Mode Register 6
Rev. 1.3, 2006-01-25
Chapter
QuadLIU
PEF 22504
Reset Value
3.7.8,
00
TM
H