pef22504 Infineon Technologies Corporation, pef22504 Datasheet - Page 243

• Manufacturer Part Number: pef22504
• Description: Quad E1/t1/j1 Line Interface Component For Long- And Short-haul Applications Pef 22504 E, Pef 22504 Ht, Version 2.1
• Manufacturer: Infineon Technologies Corporation

7
7.1
Each of the four channels of the QuadLIU
T1/J1 mode, selected by the register bit GCM2.VFREQ_EN, see
•
•
The device is programmable via one of the three integrated micro controller interfaces which are selected by
strapping of the pins IM(1:0):
•
•
•
The QuadLIU
•
•
•
All this registers can be separate into two groups:
•
•
7.2
After the device is powered up, the QuadLIU
The QuadLIU
Figure
•
•
•
•
•
•
During and after reset all internal flip-flops are reset and most of the control registers are initialized with default
values.
After reset the complete device is initialized, especially to E1 operation and “flexible master clocking mode”. The
complete initialization is listed in
IMR7 are initialized to ´FF
After reset the QuadLIU
Chapter 7.4
Data Sheet
In the so called “flexible master clocking mode” (GCM2.VFREQ_EN = ´1´) all four ports can work in E1 or in
T1 mode individually, independent from another.
In the so called “clocking fixed mode” (GCM2.VFREQ_EN = ´0´) all four ports must work together either in E1
or in T1 mode.
The asynchronous interface has two modes: Intel (IM(1:0) = ´00
interface enables byte or word access to all control and status registers, see
SPI interface (IM(1:0) = ´10
SCI interface (IM(1:0) = ´11
The control registers configure the whole device and have write and read access.
The status registers are read-only and are updated continuously. Normally, the processor reads the status
registers periodically to analyze the alarm status and signaling data.
The interrupt status registers are read-only and are cleared by reading (“rsc”). They are updated (set)
continuously. Normally, the processor reads the interrupt status registers after an interrupt occurs at pin INT.
Masking can be done with the appropriate interrupt mask registers. Mask registers are control registers.
Global registers are not belonging especially to one of the four channels. The higher address byte is ´00
The other registers are belonging to one of the four channels. The higher address bytes - marked as ´xx
the register description - are identical to the numbers 0 up to 3 of the appropriate channels. So every of this
registers exist four time in the whole device.
Needs an active clock on pin MCLK and
The pin VSEL must be connect either to 3.3 V or to V
The pins IM(1:0) must have defined values to select the micro controller interface.
Only if IM(1:0) = ´11
source address of the device.
Only if IM1 = ´1´ (SCI or SPI interface is selected) the pins D(15:5) must have defined values to configure the
central PLL in the master clocking unit of the device.
Only if IM1 = ´0´ (asynchronous micro controller interface is selected) the pin READY_EN must have a defined
value to select if the signal READY/DTACK is used
50. During reset the QuadLIU
Operational Description
Operational Overview
Device Reset
for E1 mode and
TM
TM
has three different kinds of registers:
is forced to the reset state if a low signal is input on pin RES for a minimum period of 10 s, see
b
´ (SCI interface is selected) the pins A(5:0) must have defined values to select the SCI
TM
H
´, so that not masking is performed.
must be configured first. General guidelines for configuration are described in
Chapter 7.5
b
b
´), see
´), see
Table
TM
Chapter
Chapter
74. Additionally all interrupt mask registers IMR1, IMR3, IMR4, IMR6 and
TM
for T1/J1 mode.
TM
can be operated in two clock modes, which are either E1 mode or
must be forced to the reset state first.
3.5.2.2.
3.5.2.1.
243
SS
to define if internal voltage regulator is used
Chapter
b
´) and Motorola (IM(1:0) = ´01
3.5.5:
Chapter
Operational Description
3.5.1.
Rev. 1.3, 2006-01-25
QuadLIU
PEF 22504
b
´). This
H
H
´.
´ in
TM