R8A77850ANBGV Renesas Electronics America, R8A77850ANBGV Datasheet - Page 1019

• Manufacturer Part Number: R8A77850ANBGV
• Description: IC SUPERH MPU ROMLESS 436-BGA
• Manufacturer: Renesas Electronics America
• Series: SuperH® SH7780r

Specifications of R8A77850ANBGV

• Core Processor: SH-4A
• Core Size: 32-Bit
• Speed: 600MHz
• Connectivity: Audio Codec, MMC, Serial Sound, SCI, SIO, SPI, SSI
• Peripherals: DMA, POR, WDT
• Number Of I /o: 108
• Program Memory Type: ROMless
• Ram Size: 8K x 8
• Voltage - Supply (vcc/vdd): 1 V ~ 1.2 V
• Oscillator Type: External
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 436-BGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -
• Data Converters: -

20.3.9
DWMC_CTL is in the GDTA common register block and specifies data alignment of MC output
data.
Note: For details of data alignment conversion patterns, refer to section 20.6, Data Alignment.
Initial value:
Initial value:
Bit
31 to 5 ⎯
4
3, 2
1, 0
R/W:
R/W:
BIt:
BIt:
Bit Name
DMCW_DTAM 0
DMCW_DTSA 0
DMCW_DTUA 0
GA MC Output Data Alignment Register (DWMC_CTL)
31
15
⎯
⎯
⎯
⎯
0
0
30
14
⎯
⎯
⎯
⎯
0
0
29
13
⎯
⎯
⎯
⎯
0
0
Initial
Value
All 0
28
⎯
⎯
12
⎯
⎯
0
0
R/W
⎯
R/W
R/W
R/W
27
⎯
⎯
11
⎯
⎯
0
0
26
10
⎯
⎯
⎯
⎯
0
0
Description
Reserved
These bits are always read as 0. The write value should
always be 0.
Specifies data alignment conversion mode
0: Data alignment is performed using an endian signal
1: Data alignment is performed using the DWMC_CTL
Specifies the data size for data alignment conversion.
00: No conversion
01: 64 bits
10: 32 bits
11: 16 bits
Specifies the unit for data alignment conversion.
00: No conversion
01: 8 bits
10: 16 bits
11: 32 bits
register setting
25
⎯
⎯
⎯
⎯
0
9
0
24
⎯
⎯
⎯
⎯
0
8
0
20. Graphics Data Translation Accelerator (GDTA)
23
⎯
⎯
⎯
⎯
0
7
0
Rev.1.00 Jan. 10, 2008 Page 987 of 1658
22
⎯
⎯
⎯
⎯
0
6
0
21
⎯
⎯
⎯
⎯
0
5
0
DMCW_
DTAM
R/W
20
⎯
⎯
0
4
0
DMCW_DTSA
R/W
19
⎯
⎯
0
3
0
REJ09B0261-0100
R/W
18
⎯
⎯
0
2
0
DMCW_DTUA
R/W
17
⎯
⎯
0
1
0
R/W
16
⎯
⎯
0
0
0