R8A77850ANBGV Renesas Electronics America, R8A77850ANBGV Datasheet - Page 1212

• Manufacturer Part Number: R8A77850ANBGV
• Description: IC SUPERH MPU ROMLESS 436-BGA
• Manufacturer: Renesas Electronics America
• Series: SuperH® SH7780r

Specifications of R8A77850ANBGV

• Core Processor: SH-4A
• Core Size: 32-Bit
• Speed: 600MHz
• Connectivity: Audio Codec, MMC, Serial Sound, SCI, SIO, SPI, SSI
• Peripherals: DMA, POR, WDT
• Number Of I /o: 108
• Program Memory Type: ROMless
• Ram Size: 8K x 8
• Voltage - Supply (vcc/vdd): 1 V ~ 1.2 V
• Oscillator Type: External
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 436-BGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -
• Data Converters: -

24. Multimedia Card Interface (MMCIF)
Rev.1.00 Jan. 10, 2008 Page 1180 of 1658
REJ09B0261-0100
Bit
6
5
4
3 to 0
Bit Name
—
RD_CONTI 0
DATAEN
—
Initial
Value
0
0
All 0
R/W
R
R/W
R/W
R
Description
Reserved
This bit is always read as 0. The write value should
always be 0.
Read Continue
Read data reception is resumed when 1 is written while
the sequence has been halted by FIFO full or
termination of block reading in multiple block read.
This bit is cleared to 0 automatically when 1 is written
and the MMCIF received the RD_CONTI command.
Write enabled period: While read data reception is
halted
Write of 0: Operation is not affected.
Write of 1: Resumes read data reception.
Note: Do not write to this bit out of the write enable
Data Enable
Starts a write data transmission by a command with
write data. This bit is cleared automatically when 1 is
written and the MMCIF received the DATAEN
command. Resumes write data transmission while the
sequence has been halted by FIFO empty or
termination of block writing in multiple block write.
Write enabled period: (1) after receiving a response to a
command with write data, (2) while sequence is halted
by FIFO empty, (3) when one block writing in multiple
block write is terminated.
Write of 0: Operation is not affected.
Write of 1: Starts or resumes write data transmission.
Note: Do not write to this bit out of the write enable
Reserved
These bits are always read as 0. The write value should
always be 0.
period.
period.