R8A77850ANBGV Renesas Electronics America, R8A77850ANBGV Datasheet - Page 990

IC SUPERH MPU ROMLESS 436-BGA

R8A77850ANBGV

Manufacturer Part Number
R8A77850ANBGV
Description
IC SUPERH MPU ROMLESS 436-BGA
Manufacturer
Renesas Electronics America
Series
SuperH® SH7780r
Datasheet

Specifications of R8A77850ANBGV

Core Processor
SH-4A
Core Size
32-Bit
Speed
600MHz
Connectivity
Audio Codec, MMC, Serial Sound, SCI, SIO, SPI, SSI
Peripherals
DMA, POR, WDT
Number Of I /o
108
Program Memory Type
ROMless
Ram Size
8K x 8
Voltage - Supply (vcc/vdd)
1 V ~ 1.2 V
Oscillator Type
External
Operating Temperature
-20°C ~ 75°C
Package / Case
436-BGA
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Program Memory Size
-
Data Converters
-

Available stocks

Company
Part Number
Manufacturer
Quantity
Price
Part Number:
R8A77850ANBGV
Manufacturer:
Renesas Electronics America
Quantity:
10 000
19. Display Unit (DU)
Table 19.14 Correspondence Table of Settings of Display Timing Generation Registers
Notes: The numerical values in the above table are decimal numbers.
Rev.1.00 Jan. 10, 2008 Page 958 of 1658
REJ09B0261-0100
Register Name
Horizontal display start position
register (HDSR)
Horizontal display end position
register (HDER)
Vertical display start position register
(VDSR)
Vertical display end position register
(VDER)
Horizontal synchronous pulse width
register (HSWR)
Horizontal scan period register
(HCR)
Vertical synchronous position
register (VSPR)
Vertical scan period register (VCR)
DCLKIN(input)
HSYNC( input)
DCLKOUT(output)
DR5-DR0(output)
DG5-DG0(output)
DB5-DB0(output)
1. In all scan modes, VDS, VDE, VSP, VC settings are in single-field units.
2. The values of HDS and HDE are from the fourth rising edge of DCLKOUT after
3. VDS should be set to 1 or greater.
4. HC should be set so as to satisfy HC > HDE.
detection of the falling edge of HSYNC through the rising edge of DCLKOUT.
Bit Name
HDS
HDE
VDS
VDE
HSW
HC
VSP
VC
hsw + xs - 19
hsw + xs – 19 + xw
ys – 2 *
hsw - 1
vc – vsw - 1
Master Mode
ys – 2 + yw
hc - 1
vc - 1
hsw + xs
3
Synchronization Method
TV Sync Mode
hsw + xs – 24 *
hsw + xs – 24 + xw *
ys – 2 *
ys – 2 + yw
hsw - 1
hc - 1
vc – vsw - 1
vc - 1
D0
3
D1
2
D2
2

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