R8A77850ANBGV Renesas Electronics America, R8A77850ANBGV Datasheet - Page 890

• Manufacturer Part Number: R8A77850ANBGV
• Description: IC SUPERH MPU ROMLESS 436-BGA
• Manufacturer: Renesas Electronics America
• Series: SuperH® SH7780r

Specifications of R8A77850ANBGV

• Core Processor: SH-4A
• Core Size: 32-Bit
• Speed: 600MHz
• Connectivity: Audio Codec, MMC, Serial Sound, SCI, SIO, SPI, SSI
• Peripherals: DMA, POR, WDT
• Number Of I /o: 108
• Program Memory Type: ROMless
• Ram Size: 8K x 8
• Voltage - Supply (vcc/vdd): 1 V ~ 1.2 V
• Oscillator Type: External
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 436-BGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -
• Data Converters: -

19. Display Unit (DU)
Rev.1.00 Jan. 10, 2008 Page 858 of 1658
REJ09B0261-0100
Bit
18
17
16
15 to 0
Bit Name
⎯
CP3CE
CP2CE
CP1CE
Initial
Value
0
0
0
All 0
R/W
R/W
R/W
R/W
R
Internal
Update
Yes
Yes
Yes
⎯
Description
Color Palette 3 Change Enable
0: Switching of color palette 3 is not performed.
1: Switching of color palette 3 is performed.
Color Palette 2 Change Enable
0: Switching of color palette 2 is not performed.
1: Switching of color palette 2 is performed.
Color Palette 1 Change Enable
0: Switching of color palette 1 is not performed.
1: Switching of color palette 1 is performed.
Reserved
These bits are always read as 0. The write value
should always be 0.
Switching is performed when the DRES bit in
DSYSR is changed from 1 to 0, or with the
timing of an internal update. This bit can only
be set to 1; an operation to set the bit to 0 is
invalid. After switching of the color palette 3,
the bit is cleared to 0.
When setting to 1 and clearing occur
simultaneously, clearing to 0 takes priority.
Switching is performed when the DRES bit in
DSYSR is changed from 1 to 0, or with the
timing of an internal update. This bit can only
be set to 1; an operation to set the bit to 0 is
invalid. After switching of the color palette 2,
the bit is cleared to 0.
When setting to 1 and clearing occur
simultaneously, clearing to 0 takes priority.
Switching is performed when the DRES bit in
DSYSR is changed from 1 to 0, or with the
timing of an internal update. This bit can only
be set to 1; an operation to set the bit to 0 is
invalid. After switching of the color palette 1,
the bit is cleared to 0.
When setting to 1 and clearing occur
simultaneously, clearing to 0 takes priority.