R8A77850ANBGV Renesas Electronics America, R8A77850ANBGV Datasheet - Page 1338

• Manufacturer Part Number: R8A77850ANBGV
• Description: IC SUPERH MPU ROMLESS 436-BGA
• Manufacturer: Renesas Electronics America
• Series: SuperH® SH7780r

Specifications of R8A77850ANBGV

• Core Processor: SH-4A
• Core Size: 32-Bit
• Speed: 600MHz
• Connectivity: Audio Codec, MMC, Serial Sound, SCI, SIO, SPI, SSI
• Peripherals: DMA, POR, WDT
• Number Of I /o: 108
• Program Memory Type: ROMless
• Ram Size: 8K x 8
• Voltage - Supply (vcc/vdd): 1 V ~ 1.2 V
• Oscillator Type: External
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 436-BGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -
• Data Converters: -

26. Serial Sound Interface (SSI) Module
Rev.1.00 Jan. 10, 2008 Page 1306 of 1658
REJ09B0261-0100
Bit
8
7
6 to 4
3
Bit Name
DEL
BREN
CKDV2
CKDV2
CKDV0
MUEN
Initial
Value
0
0
0
0
0
0
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Description
Serial Data Delay
Set this bit to 1, if CPEN=1
0: 1 clock cycle delay between SSI_WS and
1: No delay between SSI_WS and SSI_SDATA
Burst Mode Enable
0: Burst mode is disabled.
1: Burst mode is enabled.
Burst mode is used only in compressed mode (CPEN =
1) and transmit mode. When burst mode is enabled the
SSI_SCK signal is gated. Clock pulses are output only
when there is valid serial data being output on
SSI_SDATA.
Serial Oversampling Clock Division Ratio
These bits define the division ratio between
oversampling clock (SSI_CLK) and the serial bit clock
(SSI_SCK).
These bits are ignored if SCKD = 0.
The serial bit clock is used for the shift register and is
provided on the SSI_SCK pin.
000: (Serial bit clock frequency = oversampling clock frequency/1)
001: (Serial bit clock frequency = oversampling clock frequency/2)
010: (Serial bit clock frequency = oversampling clock frequency/4)
011: (Serial bit clock frequency = oversampling clock frequency/8)
100: (Serial bit clock frequency = oversampling clock frequency/16)
101: (Serial bit clock frequency = oversampling clock frequency/6)
110: (Serial bit clock frequency = oversampling clock frequency/12)
111: Setting prohibited
Mute Enable
0: The SSI module is not muted
1: The SSI module is muted
When the SSI module is muted in transmit mode, the
SSIn_SDATA pin is always low regardless of the
padding polarity selected.
SSI_SDATA