R8A77850ANBGV Renesas Electronics America, R8A77850ANBGV Datasheet - Page 261

• Manufacturer Part Number: R8A77850ANBGV
• Description: IC SUPERH MPU ROMLESS 436-BGA
• Manufacturer: Renesas Electronics America
• Series: SuperH® SH7780r

Specifications of R8A77850ANBGV

• Core Processor: SH-4A
• Core Size: 32-Bit
• Speed: 600MHz
• Connectivity: Audio Codec, MMC, Serial Sound, SCI, SIO, SPI, SSI
• Peripherals: DMA, POR, WDT
• Number Of I /o: 108
• Program Memory Type: ROMless
• Ram Size: 8K x 8
• Voltage - Supply (vcc/vdd): 1 V ~ 1.2 V
• Oscillator Type: External
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 436-BGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -
• Data Converters: -

8.5
8.5.1
(1)
Coherency between cache and external memory should be assured by software. In this LSI, the
following six instructions are supported for cache operations. Details of these instructions are
given in section 11, Instruction Descriptions of the SH-4A Extended Functions Software Manual.
• Operand cache invalidate instruction: OCBI @Rn
• Operand cache purge instruction: OCBP @Rn
• Operand cache write-back instruction: OCBWB @Rn
• Operand cache allocate instruction: MOVCA.L R0,@Rn
• Instruction cache invalidate instruction: ICBI @Rn
• Operand access synchronization instruction: SYNCO
(2)
The operand cache can receive "PURGE" and "FLUSH" transaction from SuperHyway bus to
control the cache coherency. Since the address used by the PURGE and FLUSH transaction is a
physical address, do not use the 1 Kbyte page size to avoid cache synonym problem in MMU
enable mode.
• PURGE transaction
Operand cache invalidation (no write-back)
Operand cache invalidation (with write-back)
Operand cache write-back
Operand cache allocation
Instruction cache invalidation
Wait for data transfer completion
When the operand cache is enabled, the PURGE transaction checks the operand cache and
invalidates the hit entry. If the invalidated entry is dirty, the data is written back to the external
memory. If the transaction is not hit to the cache, it is no-operation.
Cache Operation Instruction
Coherency Control
Cache Operation Instruction
Coherency between Cache and External Memory
Rev.1.00 Jan. 10, 2008 Page 229 of 1658
REJ09B0261-0100
8. Caches