R8A77850ANBGV Renesas Electronics America, R8A77850ANBGV Datasheet - Page 27

• Manufacturer Part Number: R8A77850ANBGV
• Description: IC SUPERH MPU ROMLESS 436-BGA
• Manufacturer: Renesas Electronics America
• Series: SuperH® SH7780r

Specifications of R8A77850ANBGV

• Core Processor: SH-4A
• Core Size: 32-Bit
• Speed: 600MHz
• Connectivity: Audio Codec, MMC, Serial Sound, SCI, SIO, SPI, SSI
• Peripherals: DMA, POR, WDT
• Number Of I /o: 108
• Program Memory Type: ROMless
• Ram Size: 8K x 8
• Voltage - Supply (vcc/vdd): 1 V ~ 1.2 V
• Oscillator Type: External
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 436-BGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -
• Data Converters: -

24.5 MMCIF Interrupt Sources................................................................................................ 1239
24.6 Operations when Using DMA.......................................................................................... 1240
24.7 Register Accesses with Little Endian Specification......................................................... 1261
Section 25 Audio Codec Interface (HAC)
25.1 Features............................................................................................................................ 1263
25.2 Input/Output Pins ............................................................................................................. 1265
25.3 Register Descriptions ....................................................................................................... 1266
25.4 AC 97 Frame Slot Structure............................................................................................. 1286
25.5 Operation ......................................................................................................................... 1288
Section 26 Serial Sound Interface (SSI) Module
26.1 Features............................................................................................................................ 1297
26.2 Input/Output Pins ............................................................................................................. 1299
26.3 Register Descriptions ....................................................................................................... 1300
24.4.1
24.6.1
24.6.2
25.3.1
25.3.2
25.3.3
25.3.4
25.3.5
25.3.6
25.3.7
25.3.8
25.3.9
25.3.10 HAC Control Register (HACACR) .................................................................. 1284
25.5.1
25.5.2
25.5.3
25.5.4
25.5.5
25.5.6
25.5.7
25.5.8
26.3.1
26.3.2
26.3.3
26.3.4
Operations in MMC Mode................................................................................ 1209
Operation in Read Sequence............................................................................. 1240
Operation in Write Sequence ............................................................................ 1250
Control and Status Register (HACCR) ............................................................. 1269
Command/Status Address Register (HACCSAR) ............................................ 1271
Command/Status Data Register (HACCSDR).................................................. 1273
PCM Left Channel Register (HACPCML)....................................................... 1275
PCM Right Channel Register (HACPCMR) .................................................... 1277
TX Interrupt Enable Register (HACTIER)....................................................... 1278
TX Status Register (HACTSR)......................................................................... 1279
RX Interrupt Enable Register (HACRIER) ...................................................... 1281
RX Status Register (HACRSR) ........................................................................ 1282
Receiver ............................................................................................................ 1288
Transmitter........................................................................................................ 1288
DMA................................................................................................................. 1289
Interrupts........................................................................................................... 1289
Initialization Sequence...................................................................................... 1290
Power-Down Mode........................................................................................... 1295
Notes................................................................................................................. 1295
Reference .......................................................................................................... 1295
Control Register (SSICR) ................................................................................. 1301
Status Register (SSISR) .................................................................................... 1308
Transmit Data Register (SSITDR).................................................................... 1313
Receive Data Register (SSIRDR) ..................................................................... 1313
.................................................................. 1263
...................................................... 1297
Rev.1.00 Jan. 10, 2008 Page xxv of xxx
REJ09B0261-0100