R8A77850ANBGV Renesas Electronics America, R8A77850ANBGV Datasheet - Page 594

• Manufacturer Part Number: R8A77850ANBGV
• Description: IC SUPERH MPU ROMLESS 436-BGA
• Manufacturer: Renesas Electronics America
• Series: SuperH® SH7780r

Specifications of R8A77850ANBGV

• Core Processor: SH-4A
• Core Size: 32-Bit
• Speed: 600MHz
• Connectivity: Audio Codec, MMC, Serial Sound, SCI, SIO, SPI, SSI
• Peripherals: DMA, POR, WDT
• Number Of I /o: 108
• Program Memory Type: ROMless
• Ram Size: 8K x 8
• Voltage - Supply (vcc/vdd): 1 V ~ 1.2 V
• Oscillator Type: External
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 436-BGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -
• Data Converters: -

13. PCI Controller (PCIC)
13.3.1
PCIECR is a register that specifies whether the PCIC is valid or invalid.
Rev.1.00 Jan. 10, 2008 Page 562 of 1658
REJ09B0261-0100
Initial value:
Initial value:
Bit
31 to 1
0
PCI R/W:
PCI R/W:
SH R/W:
SH R/W:
Bit:
Bit:
PCIC Enable Control Register (PCIECR)
Bit Name
—
ENBL
31
15
—
—
—
—
R
R
0
0
30
—
—
14
—
—
R
R
0
0
Initial
Value
All 0
0
29
—
—
13
—
—
R
R
0
0
28
12
—
—
—
—
R
R
0
0
R/W
SH: R
PCI: ⎯
SH: R/W
PCI: ⎯
27
11
—
—
—
—
R
R
0
0
26
10
—
—
—
—
R
R
0
0
Description
Reserved
These bits are always read as 0. The write value
should always be 0.
PCI Enable Bit.
Enables (validates) the PCIC. When this bit is 0, the
PCIC is disabled and the access from the CPU to the
PCIC, or from the external PCI device to the PCIC is
invalid (the PCIECR can be accessed). The access
from other CPU is invalid during writing and undefined
during reading. The access from the external PCI
device cannot be accepted).
0: PCIC disabled
1: PCIC enabled
25
—
—
—
—
R
R
0
9
0
24
—
—
—
—
R
R
0
8
0
23
—
—
—
—
R
R
0
7
0
22
—
—
—
—
R
R
0
6
0
21
—
—
—
—
R
R
0
5
0
20
—
—
—
—
R
R
0
4
0
19
—
—
—
—
R
R
0
3
0
18
—
—
—
—
R
R
0
2
0
17
—
—
—
—
R
R
0
1
0
ENBL
R/W
16
—
—
—
R
0
0
0