R8A77850ANBGV Renesas Electronics America, R8A77850ANBGV Datasheet - Page 1490

IC SUPERH MPU ROMLESS 436-BGA

R8A77850ANBGV

Manufacturer Part Number
R8A77850ANBGV
Description
IC SUPERH MPU ROMLESS 436-BGA
Manufacturer
Renesas Electronics America
Series
SuperH® SH7780r
Datasheet

Specifications of R8A77850ANBGV

Core Processor
SH-4A
Core Size
32-Bit
Speed
600MHz
Connectivity
Audio Codec, MMC, Serial Sound, SCI, SIO, SPI, SSI
Peripherals
DMA, POR, WDT
Number Of I /o
108
Program Memory Type
ROMless
Ram Size
8K x 8
Voltage - Supply (vcc/vdd)
1 V ~ 1.2 V
Oscillator Type
External
Operating Temperature
-20°C ~ 75°C
Package / Case
436-BGA
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Program Memory Size
-
Data Converters
-

Available stocks

Company
Part Number
Manufacturer
Quantity
Price
Part Number:
R8A77850ANBGV
Manufacturer:
Renesas Electronics America
Quantity:
10 000
29. User Break Controller (UBC)
Rev.1.00 Jan. 10, 2008 Page 1458 of 1658
REJ09B0261-0100
Bit
29 to 24 MFI
23 to 16 AIV
15
14 to 12 SZ
11 to 8
Bit Name
Initial
Value
100000
All 0
0
All 0
All 0
R/W
R/W
R/W
R
R/W
R
Description
Match Flag Specify
Specifies the match flag to be included in the match
conditions.
000000: MF0 bit of the CCMFR register
000001: MF1 bit of the CCMFR register
Others: Reserved (setting prohibited)
Note: The initial value is the reserved value, but when 1
ASID Specify
Specifies the ASID value to be included in the match
conditions.
Reserved
For read/write in this bit, refer to General Precautions on
Handling of Product.
Operand Size Select
Specifies the operand size to be included in the match
conditions. This bit is valid only when the operand
access cycle is specified as a match condition.
000: The operand size is not included in the match
conditions; thus, not checked (any operand size
specifies the match condition).*
001: Byte access
010: Word access
011: Longword access
100: Quadword access*
Others: Reserved (setting prohibited)
Reserved
For read/write in this bit, refer to General Precautions on
Handling of Product.
is written into CBR0[0], MFI must be set to 000000
or 000001. And note that the channel 0 is not hit
when MFE bit of this register is 1 and MFI bits are
000000 in the condition of CCRMF.MF0 = 0.
2
1

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