R8A77850ANBGV Renesas Electronics America, R8A77850ANBGV Datasheet - Page 97

• Manufacturer Part Number: R8A77850ANBGV
• Description: IC SUPERH MPU ROMLESS 436-BGA
• Manufacturer: Renesas Electronics America
• Series: SuperH® SH7780r

Specifications of R8A77850ANBGV

• Core Processor: SH-4A
• Core Size: 32-Bit
• Speed: 600MHz
• Connectivity: Audio Codec, MMC, Serial Sound, SCI, SIO, SPI, SSI
• Peripherals: DMA, POR, WDT
• Number Of I /o: 108
• Program Memory Type: ROMless
• Ram Size: 8K x 8
• Voltage - Supply (vcc/vdd): 1 V ~ 1.2 V
• Oscillator Type: External
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 436-BGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -
• Data Converters: -

This LSI is a 2-ILP (instruction-level-parallelism) superscalar pipelining microprocessor.
Instruction execution is pipelined, and two instructions can be executed in parallel.
4.1
Figure 4.1 shows the basic pipelines. Normally, a pipeline consists of eight stages: instruction
fetch (I1/I2/I3), decode and register read (ID), execution (E1/E2/E3), and write-back (WB). An
instruction is executed as a combination of basic pipelines.
1. General Pipeline
2. General Load/Store Pipeline
3. Special Pipeline
4. Special Load/Store Pipeline
5. Floating-Point Pipeline
6.
-
Pipelines
Instruction fetch
-
Floating-Point Extended Pipeline
-
-
-
Instruction fetch
-
Instruction fetch
Instruction fetch
Instruction fetch
Instruction fetch
I1
I1
I1
I1
I1
I1
I2
I2
I2
I2
I2
I2
-
Predecode
-
I3
Predecode
-
-
-
-
Predecode
Predecode
Predecode
Predecode
Section 4 Pipelining
I3
-Instruction
-Issue
decode
I3
I3
I3
I3
Figure 4.1 Basic Pipelines
ID
-
-
decode
Instruction
Issue
-
decode
-
-
-
-
-
-
-
-
-Register read
-Forwarding
-
decode
-
-
Instruction
Issue
Register read
Instruction
decode
Issue
Register read
Instruction
decode
Issue
Register read
Instruction
Issue
Register read
ID
FE1
ID
ID
ID
ID
-
-
Register read
Forwarding
-
Operation
FE2
FS1
-
-
-
Forwarding
Forwarding
Address
calculation
E1
E1
E1
E1
-
Operation
-
Operation
FE3
FS2
-
-
-
Operation
Memory data access
Operation
Rev.1.00 Jan. 10, 2008 Page 65 of 1658
-
Operation
FE4
E2
E2
E2
E2
-
Operation
FS3
-
Operation
FE5
-
Operation
E3
E3
E3
E3
FS4
-
Operation
FE6
-
-
-
Write-back
Write-back
Write-back
REJ09B0261-0100
-
-
Operation
Write-back
-
-
Operation
Write-back
WB
WB
WB
WB
FS
4. Pipelining
FS