R8A77850ANBGV Renesas Electronics America, R8A77850ANBGV Datasheet - Page 750

IC SUPERH MPU ROMLESS 436-BGA

R8A77850ANBGV

Manufacturer Part Number
R8A77850ANBGV
Description
IC SUPERH MPU ROMLESS 436-BGA
Manufacturer
Renesas Electronics America
Series
SuperH® SH7780r
Datasheet

Specifications of R8A77850ANBGV

Core Processor
SH-4A
Core Size
32-Bit
Speed
600MHz
Connectivity
Audio Codec, MMC, Serial Sound, SCI, SIO, SPI, SSI
Peripherals
DMA, POR, WDT
Number Of I /o
108
Program Memory Type
ROMless
Ram Size
8K x 8
Voltage - Supply (vcc/vdd)
1 V ~ 1.2 V
Oscillator Type
External
Operating Temperature
-20°C ~ 75°C
Package / Case
436-BGA
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Program Memory Size
-
Data Converters
-

Available stocks

Company
Part Number
Manufacturer
Quantity
Price
Part Number:
R8A77850ANBGV
Manufacturer:
Renesas Electronics America
Quantity:
10 000
14. Direct Memory Access Controller (DMAC)
Rev.1.00 Jan. 10, 2008 Page 718 of 1658
REJ09B0261-0100
Notes: 1. In repeat mode, a transfer request is acceptted with TE =1 when HIE = 1 and HE = 0
TCR – 1 → TCR, SAR, and DAR updated
Reload mode: TCRBL – 1 → TCRBL
SAR, DAR, TCR, CHCR, DMAOR
2. In auto-request mode, transfer starts when bits NMIF, AE, and TE are all 0 or bits TE
3. DREQ is level detection (external request) in burst mode or cycle-steral mode.
4. DREQ is edge detection (external request) or auto request in burst mode.
5. Loading to SAR and DAR differs according to the operating conditions in each mode.
6. TCRBH and TCRBL refer to TCRB23 to TCRB16 and TCRB7 to TCRB0 respectively.
SARB, DARB, TCRB, DMARS
Transfer (1 transfer unit);
(half end interrupt is enable and clear the HE to 0 after HE is set to 1).
and HIE are 1 and HE is 0 (in repeat mode), and bits DE and DME are set to 1.
DMINT interrupt request
Transfer request occurs?
NMIF = 1 or AE =1 or
DE = 0 or DME = 0?
TE, AE, NMIF = 0?
DE, DME = 1 and
Reload mode?
Repeat mode?
Initial settings
Normal end
Yes
Yes
Yes
No
TCR = 0?
(IE = 1)
No
No
TE = 1
Start
Figure 14.11 Flowchart of DMA Transfer
*
*
1
2
Yes
Yes
Yes
No
No
No
No
*
6
TCRB → TCR load
TCRBH → TCRBL load
HIE = 0 or HE = 1?
SARB/DARB load
SARB/DARB load
Yes
TCRBL = 0?
Yes
No
*
No
5
*
*
5
6
HE = 1, DMINT interrupt
NMIF = 1 or AE = 1 or
DE = 0 or DME = 0?
TCR = TCRB/2?
request (HIE = 1)
Transfer end
Yes
Yes
*
4
transfer request mode
Bus mode, DREQ
detection system,
No
*
3

Related parts for R8A77850ANBGV