R8A77850ANBGV Renesas Electronics America, R8A77850ANBGV Datasheet - Page 875

IC SUPERH MPU ROMLESS 436-BGA

R8A77850ANBGV

Manufacturer Part Number
R8A77850ANBGV
Description
IC SUPERH MPU ROMLESS 436-BGA
Manufacturer
Renesas Electronics America
Series
SuperH® SH7780r
Datasheet

Specifications of R8A77850ANBGV

Core Processor
SH-4A
Core Size
32-Bit
Speed
600MHz
Connectivity
Audio Codec, MMC, Serial Sound, SCI, SIO, SPI, SSI
Peripherals
DMA, POR, WDT
Number Of I /o
108
Program Memory Type
ROMless
Ram Size
8K x 8
Voltage - Supply (vcc/vdd)
1 V ~ 1.2 V
Oscillator Type
External
Operating Temperature
-20°C ~ 75°C
Package / Case
436-BGA
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Program Memory Size
-
Data Converters
-

Available stocks

Company
Part Number
Manufacturer
Quantity
Price
Part Number:
R8A77850ANBGV
Manufacturer:
Renesas Electronics America
Quantity:
10 000
Bit
9
8
Bit Name
DRES
DEN
Initial
Value
1
0
R/W
R/W
R/W
Internal
Update
None
Yes
Description
Display Reset
Display Enable
00: Starts display synchronization operation.
01: Starts display synchronization operation.
10: Halts display and synchronization operation.
However, when the ODPM bit in DSMR is 1, the
ODDF pin output is clamped.
11: Setting prohibited
3. The HSYNC, VSYNC, ODDF pins are input
pins.
In the case of a register not yet set,
unexpected operation may occur; hence
DRES should be set to 0 after setting all the
registers in the display unit (DU).
When DEN = 0, the display data is the value
set in the display-off output register (DOOR).
In the case of a register not yet set,
unexpected operation may occur; hence
DRES and DEN should be set to 0 and 1
respectively after setting all the registers in
the display unit (DU).
When DEN = 1, the display data is the value
stored in memory from the next frame.
Halts display operation and synchronization
operation. Except for the following bits in
DSSR, register settings are held.
For these settings, operation is as follows.
1. All display data output is 0.
2. The following bits in DSSR are cleared to
0.
⎯ TV sync signal error flag (TVR)
⎯ Frame flag (FRM)
⎯ Vertical blanking flag (VBK)
⎯ Raster interrupt flag (RINT)
⎯ Horizontal blanking flag (HBK)
Rev.1.00 Jan. 10, 2008 Page 843 of 1658
19. Display Unit (DU)
REJ09B0261-0100

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