R8A77850ANBGV Renesas Electronics America, R8A77850ANBGV Datasheet - Page 1503

• Manufacturer Part Number: R8A77850ANBGV
• Description: IC SUPERH MPU ROMLESS 436-BGA
• Manufacturer: Renesas Electronics America
• Series: SuperH® SH7780r

Specifications of R8A77850ANBGV

• Core Processor: SH-4A
• Core Size: 32-Bit
• Speed: 600MHz
• Connectivity: Audio Codec, MMC, Serial Sound, SCI, SIO, SPI, SSI
• Peripherals: DMA, POR, WDT
• Number Of I /o: 108
• Program Memory Type: ROMless
• Ram Size: 8K x 8
• Voltage - Supply (vcc/vdd): 1 V ~ 1.2 V
• Oscillator Type: External
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 436-BGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -
• Data Converters: -

29.2.8
CCMFR is a readable/writable 32-bit register which indicates whether or not the match conditions
have been satisfied for each channel. When a channel match condition has been satisfied, the
corresponding flag bit is set to 1. To clear the flags, write the data containing value 0 for the bits to
be cleared and value 1 for the other bits to this register. (The logical AND between the value
which has been written and the current register value is actually written to the register.) Sequential
operation using multiple channels is available by using these match flags.
Bit
31 to 2
1
0
Initial value :
Initial value :
R/W:
R/W:
Bit :
Bit :
Channel Match Flag Register (CCMFR)
Bit Name
—
MF1
MF0
31
15
R
R
0
0
30
14
R
R
0
0
Initial
Value
All 0
0
0
29
13
R
R
0
0
28
12
R
R
0
0
27
11
R
R
0
0
R/W
R
R/W
R/W
26
10
R
R
0
0
Channel 1 Condition Match Flag
Channel 0 Condition Match Flag
Description
Reserved
For read/write in this bit, refer to General Precautions
on Handling of Product.
This flag is set to 1 when the channel 1 match
condition has been satisfied. To clear the flag, write 0
to this bit.
0: Channel 1 match condition has not been satisfied.
1: Channel 1 match condition has been satisfied.
This flag is set to 1 when the channel 0 match
condition has been satisfied. To clear the flag, write 0
to this bit.
0: Channel 0 match condition has not been satisfied.
1: Channel 0 match condition has been satisfied.
25
R
R
0
9
0
24
R
R
0
8
0
23
R
R
0
7
0
Rev.1.00 Jan. 10, 2008 Page 1471 of 1658
22
R
R
6
0
0
21
R
R
0
5
0
29. User Break Controller (UBC)
20
R
R
0
4
0
19
R
R
0
3
0
REJ09B0261-0100
18
R
R
0
2
0
MF1
R/W
17
R
0
1
0
MF0
R/W
16
R
0
0
0