R8A77850ANBGV Renesas Electronics America, R8A77850ANBGV Datasheet - Page 519

IC SUPERH MPU ROMLESS 436-BGA

R8A77850ANBGV

Manufacturer Part Number
R8A77850ANBGV
Description
IC SUPERH MPU ROMLESS 436-BGA
Manufacturer
Renesas Electronics America
Series
SuperH® SH7780r
Datasheet

Specifications of R8A77850ANBGV

Core Processor
SH-4A
Core Size
32-Bit
Speed
600MHz
Connectivity
Audio Codec, MMC, Serial Sound, SCI, SIO, SPI, SSI
Peripherals
DMA, POR, WDT
Number Of I /o
108
Program Memory Type
ROMless
Ram Size
8K x 8
Voltage - Supply (vcc/vdd)
1 V ~ 1.2 V
Oscillator Type
External
Operating Temperature
-20°C ~ 75°C
Package / Case
436-BGA
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Program Memory Size
-
Data Converters
-

Available stocks

Company
Part Number
Manufacturer
Quantity
Price
Part Number:
R8A77850ANBGV
Manufacturer:
Renesas Electronics America
Quantity:
10 000
Note: Writing to this register should be performed only when the following conditions are met.
Bit
15 to 10 ⎯
9, 8
7 to 3
1, 0
Bit Name
BASFT1
and
BASFT0
BWIDTH1
and
BWIDTH0
When SDRAM access is disabled (when the ACEN bit in the DBEN register is 0.).
When automatic issue of auto-refresh is disabled (when the ARFEN bit in the
DBRFCNT0 register is cleared to 0.).
Initial
Value
All 0
00
All 0
01
R/W
R
R/W
R
R/W
Description
Reserved
These bits are always read as 0. The write value should
always be 0.
Operation when a value other than 0 is written is not
guaranteed.
These bits select the amount of shifting downward of
the bank address.
00: No shift
01: Shift the bank address downward 1 bit.
10: Shift the bank address downward 2 bits.
11: Shift the bank address downward 3 bits.
Reserved
These bits are always read as 0. The write value should
always be 0.
Operation when a value other than 0 is written is not
guaranteed.
These bits set the external data bus width.
00: Setting prohibited (If specified, correct operation
01: 16 bits
10: 32 bits
11: Setting prohibited (If specified, correct operation
Bank Address Shift Bits
SDRAM Bus Width Setting Bits
cannot be guaranteed.)
cannot be guaranteed.)
Rev.1.00 Jan. 10, 2008 Page 487 of 1658
12. DDR2-SDRAM Interface (DBSC2)
REJ09B0261-0100

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