R8A77850ANBGV Renesas Electronics America, R8A77850ANBGV Datasheet - Page 73
![IC SUPERH MPU ROMLESS 436-BGA](/photos/28/62/286211/436-bfbga_sml.jpg)
R8A77850ANBGV
Manufacturer Part Number
R8A77850ANBGV
Description
IC SUPERH MPU ROMLESS 436-BGA
Manufacturer
Renesas Electronics America
Series
SuperH® SH7780r
Datasheet
1.R8A77850AADBGV.pdf
(1694 pages)
Specifications of R8A77850ANBGV
Core Processor
SH-4A
Core Size
32-Bit
Speed
600MHz
Connectivity
Audio Codec, MMC, Serial Sound, SCI, SIO, SPI, SSI
Peripherals
DMA, POR, WDT
Number Of I /o
108
Program Memory Type
ROMless
Ram Size
8K x 8
Voltage - Supply (vcc/vdd)
1 V ~ 1.2 V
Oscillator Type
External
Operating Temperature
-20°C ~ 75°C
Package / Case
436-BGA
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Program Memory Size
-
Data Converters
-
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
R8A77850ANBGV
Manufacturer:
Renesas Electronics America
Quantity:
10 000
- Current page: 73 of 1694
- Download datasheet (9Mb)
For the 64-bit data format, see figure 2.5.
2.6
This LSI has major three processing states: the reset state, instruction execution state, and power-
down state.
(1)
In this state the CPU is reset. The reset state is divided into the power-on reset state and the
manual reset.
In the power-on reset state, the internal state of the CPU and the on-chip peripheral module
registers are initialized. In the manual reset state, the internal state of the CPU and some registers
of on-chip peripheral modules are initialized. For details, see register descriptions for each section.
(2)
In this state, the CPU executes program instructions in sequence. The Instruction execution state
has the normal program execution state and the exception handling state.
(3)
In a power-down state, CPU halts operation and power consumption is reduced. The power-down
state is entered by executing a SLEEP instruction. There are two modes in the power-down state:
sleep mode and standby mode. For details, see section 17, Power-Down mode.
Reset State
Instruction Execution State
Power-Down State
Processing States
Address A + 4
Address A + 8
Address A
7
31
31
15
Byte 0
A
Word 0
0 7
23
Byte 1 Byte 2 Byte 3
Figure 2.7 Data Formats in Memory
A + 1
Big endian
Longword
0 7
0 15
15
A + 2
Word 1
0 7
7
A + 3
0
0
0
0
7
31
31
15
A + 11
Byte 3
Word 1
0 7
23
A + 10 A + 9
Byte 2 Byte 1 Byte 0
Little endian
Longword
Rev.1.00 Jan. 10, 2008 Page 41 of 1658
0 7
0
15
15
Word 0
0 7
7
A + 8
0
0
0
0
Address A + 8
Address A + 4
Address A
2. Programming Model
REJ09B0261-0100
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