R8A77850ANBGV Renesas Electronics America, R8A77850ANBGV Datasheet - Page 245

• Manufacturer Part Number: R8A77850ANBGV
• Description: IC SUPERH MPU ROMLESS 436-BGA
• Manufacturer: Renesas Electronics America
• Series: SuperH® SH7780r

Specifications of R8A77850ANBGV

• Core Processor: SH-4A
• Core Size: 32-Bit
• Speed: 600MHz
• Connectivity: Audio Codec, MMC, Serial Sound, SCI, SIO, SPI, SSI
• Peripherals: DMA, POR, WDT
• Number Of I /o: 108
• Program Memory Type: ROMless
• Ram Size: 8K x 8
• Voltage - Supply (vcc/vdd): 1 V ~ 1.2 V
• Oscillator Type: External
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 436-BGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -
• Data Converters: -

• Tag
• V bit (validity bit)
• U bit (dirty bit)
Stores the upper 19 bits of the 29-bit physical address of the data line to be cached. The tag is
not initialized by a power-on or manual reset.
Indicates that valid data is stored in the cache line. When this bit is 1, the cache line data is
valid. The V bit is initialized to 0 by a power-on reset, but retains its value in a manual reset.
The U bit is set to 1 if data is written to the cache line while the cache is being used in copy-
back mode. That is, the U bit indicates a mismatch between the data in the cache line and the
data in external memory. The U bit is never set to 1 while the cache is being used in write-
through mode, unless it is modified by accessing the memory-mapped cache (see section 8.6,
Memory-Mapped Cache Configuration). The U bit is initialized to 0 by a power-on reset, but
retains its value in a manual reset.
Virtual address
31
22
19
MMU
Figure 8.2 Configuration of Instruction Cache (Cache size = 32 Kbytes)
8
Entry selection
255
0
(way 0 to way 3)
Address array
19 bits
Comparison
Tag
Hit signal
(Way 0 to way 3)
1 bit
V
3
13 12
32 bits
LW0
32 bits
LW1
10
32 bits
LW2
[12:5]
Rev.1.00 Jan. 10, 2008 Page 213 of 1658
(way 0 to way3)
32 bits
Read data
LW3
Data array
5 4
32 bits
LW4
Longword (LW) selection
2
32 bits
LW5
0
32 bits
LW6
32 bits
REJ09B0261-0100
LW7
8. Caches
LRU
6 bits