R8A77850ANBGV Renesas Electronics America, R8A77850ANBGV Datasheet - Page 698

• Manufacturer Part Number: R8A77850ANBGV
• Description: IC SUPERH MPU ROMLESS 436-BGA
• Manufacturer: Renesas Electronics America
• Series: SuperH® SH7780r

Specifications of R8A77850ANBGV

• Core Processor: SH-4A
• Core Size: 32-Bit
• Speed: 600MHz
• Connectivity: Audio Codec, MMC, Serial Sound, SCI, SIO, SPI, SSI
• Peripherals: DMA, POR, WDT
• Number Of I /o: 108
• Program Memory Type: ROMless
• Ram Size: 8K x 8
• Voltage - Supply (vcc/vdd): 1 V ~ 1.2 V
• Oscillator Type: External
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 436-BGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -
• Data Converters: -

14. Direct Memory Access Controller (DMAC)
Figure 14.1 shows a block diagram of the DMAC.
Rev.1.00 Jan. 10, 2008 Page 666 of 1658
REJ09B0261-0100
External ROM
External RAM
Interrupt controller
DREQ0 to DREQ3
DRAK0 to DRAK3
DACK0 to DACK3
External I/O
Legend:
SAR0 to SAR11:
SARB0 to SARB3, SARB6 to SARB11:
DAR0 to DAR11:
DARB0 to DARB3, DARB6 to DARB9:
TCR0 to TCR11:
TCRB0 to TCRB3, TCRB6 to TCRB9:
CHCR0 to CHCR11:
DMAOR0 and DMAOR1:
DMARS0 to DMARS5:
DMINT0 to DMINT11:
DMAE0:
DMAE1:
Note: * The half-end interrupt request is valid for only channels 0 to 3 and channels 6 to 9.
peripheral
On-chip
memory
On-chip
module
DMA transfer end signal
DMA transfer request signal
bus controller
Peripheral
DMINT0 to DMINT11
DMAE0
DMAE1
DDRIF
LBSC
PCIC
Figure 14.1 Block Diagram of DMAC
DMA source address register
DMA source address register B
DMA destination address register
DMA destination address register B
DMA transfer count register
DMA transfer count register B
DMA channel control register
DMA operation register
DMA extended resource register
DMA transfer end/half-end interrupt request*
channels 0 to 5 address error interrupt request
channels 6 to 11 address error interrupt request
DMAC channels 0 to 5
DMAC channels 6 to 11
interface
interface
Register
Request
Bus
Register
Request
Bus
Iteration
Start-up
Iteration
Start-up
control
control
control
priority
control
control
control
control
priority
control
DMARS0 to DMARS2
DMARS3 to DMARS5
CHCR6 to CHCR11
CHCR0 to CHCR5
SARB0 to SARB3
DARB0 to DARB3
SARB6 to SARB9
DARB6 to DARB9
TCRB0 to TCRB3
TCRB6 to TCRB9
SAR6 to SAR11
DAR6 to DAR11
TCR6 to TCR11
DAR0 to DAR5
SAR0 to SAR5
TCR0 to TCR5
DMAOR0
DMAOR1