R8A77850ANBGV Renesas Electronics America, R8A77850ANBGV Datasheet - Page 237

• Manufacturer Part Number: R8A77850ANBGV
• Description: IC SUPERH MPU ROMLESS 436-BGA
• Manufacturer: Renesas Electronics America
• Series: SuperH® SH7780r

Specifications of R8A77850ANBGV

• Core Processor: SH-4A
• Core Size: 32-Bit
• Speed: 600MHz
• Connectivity: Audio Codec, MMC, Serial Sound, SCI, SIO, SPI, SSI
• Peripherals: DMA, POR, WDT
• Number Of I /o: 108
• Program Memory Type: ROMless
• Ram Size: 8K x 8
• Voltage - Supply (vcc/vdd): 1 V ~ 1.2 V
• Oscillator Type: External
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 436-BGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -
• Data Converters: -

(2)
The PPN field in the ITLB is extended to bits 31 to 10.
(3)
The PPN field in the UTLB is extended to bits 31 to 10. The same UB bit as that in the PMB is
added in each entry of the UTLB.
• UB: Buffered write bit
In a memory-mapped TLB access, the UB bit can be read from or written to by bit 9 in the data
array.
(4)
The same UB bit as that in the PMB is added in bit 9 in PTEL. This UB bit is written to the UB bit
in the UTLB by the LDTLB instruction. The PPN field is extended to bits 31 to 10.
Bit
30 to 8
7 to 0
Specifies whether a buffered write is performed.
0: Buffered write (Subsequent processing proceeds without waiting for the write to complete.)
1: Unbuffered write (Subsequent processing is stalled until the write has completed.)
ITLB
UTLB
PTEL
Bit Name
⎯
UB
Initial
Value
All 0
All 0
R/W
R
R/W
Description
Reserved
For details on reading from or writing to these bits, see
description in General Precautions on Handling of
Product.
Buffered Write Control for Each Area (64 Mbytes)
When writing is performed without using the cache or in
the cache write-through mode, these bits specify
whether the CPU waits for the end of writing for each
area.
0: The CPU does not wait for the end of writing
1: The CPU stalls and waits for the end of writing
UB[7]: Corresponding to the control register area
UB[6:0]: These bits are invalid in 32-bit address
extended mode.
Rev.1.00 Jan. 10, 2008 Page 205 of 1658
7. Memory Management Unit (MMU)
REJ09B0261-0100