R8A77850ANBGV Renesas Electronics America, R8A77850ANBGV Datasheet - Page 1138

• Manufacturer Part Number: R8A77850ANBGV
• Description: IC SUPERH MPU ROMLESS 436-BGA
• Manufacturer: Renesas Electronics America
• Series: SuperH® SH7780r

Specifications of R8A77850ANBGV

• Core Processor: SH-4A
• Core Size: 32-Bit
• Speed: 600MHz
• Connectivity: Audio Codec, MMC, Serial Sound, SCI, SIO, SPI, SSI
• Peripherals: DMA, POR, WDT
• Number Of I /o: 108
• Program Memory Type: ROMless
• Ram Size: 8K x 8
• Voltage - Supply (vcc/vdd): 1 V ~ 1.2 V
• Oscillator Type: External
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 436-BGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -
• Data Converters: -

22. Serial I/O with FIFO (SIOF)
22.3.2
SICTR is a 16-bit readable/writable register that sets the SIOF operating state.
Rev.1.00 Jan. 10, 2008 Page 1106 of 1658
REJ09B0261-0100
Initial value:
Bit
15
14
13 to 10 ⎯
9
R/W:
BIt:
Control Register (SICTR)
Bit Name
SCKE
FSE
TXE
SCKE FSE
R/W
15
0
R/W
14
0
13
—
R
0
Initial
Value
0
0
All 0
0
12
—
R
0
R/W
R/W
R/W
R
R/W
11
—
R
0
10
—
R
0
Description
Serial Clock Output Enable
This bit is valid in master mode.
0: Disables the SIOF_SCK output (outputs low level)
1: Enables the SIOF_SCK output
If this bit is set to 1, the SIOF initializes the baud rate
generator and initiates the operation. At the same time,
the SIOF outputs the clock generated by the baud rate
generator to the SIOF_SCK pin.
Frame Synchronous Signal Output Enable
This bit is valid in master mode.
0: Disables the SIOF_SYNC output (outputs low level)
1: Enables the SIOF_SYNC output
If this bit is set to 1, the SIOF initializes the frame
counter and initiates the operation.
Reserved
These bits are always read as 0. The write value should
always be 0.
Transmit Enable
0: Disables data transmission from the SIOF_TXD pin
(Outputs according to the value set in the TXDIZ bit)
1: Enables data transmission from the SIOF_TXD pin
•
•
•
TXE
R/W
9
0
This bit setting becomes valid at the start of the next
frame (at the rising edge of the SIOF_SYNC signal).
When the 1 setting for this bit becomes valid, the
SIOF issues a transmit transfer request according to
the setting of the TFWM bit in SIFCTR. When
transmit data is stored in the transmit FIFO,
transmission of data from the SIOF_TXD pin begins.
This bit is initialized by a transmit reset.
RXE
R/W
8
0
—
R
7
0
—
R
6
0
—
R
5
0
—
R
4
0
—
R
3
0
—
R
2
0
TXRST
R/W
1
0
RXRST
R/W
0
0