R8A77850ANBGV Renesas Electronics America, R8A77850ANBGV Datasheet - Page 230

• Manufacturer Part Number: R8A77850ANBGV
• Description: IC SUPERH MPU ROMLESS 436-BGA
• Manufacturer: Renesas Electronics America
• Series: SuperH® SH7780r

Specifications of R8A77850ANBGV

• Core Processor: SH-4A
• Core Size: 32-Bit
• Speed: 600MHz
• Connectivity: Audio Codec, MMC, Serial Sound, SCI, SIO, SPI, SSI
• Peripherals: DMA, POR, WDT
• Number Of I /o: 108
• Program Memory Type: ROMless
• Ram Size: 8K x 8
• Voltage - Supply (vcc/vdd): 1 V ~ 1.2 V
• Oscillator Type: External
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 436-BGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -
• Data Converters: -

7. Memory Management Unit (MMU)
(2)
The UTLB data array is allocated to addresses H'F780 0000 to H'F78F FFFF in the P4 area.
Access to data array 2 requires a 32-bit address field specification (when reading or writing) and a
32-bit data field specification (when writing). Information for selecting the entry to be accessed is
specified in the address field, and EPR and ESZ to be written to data array 2 are specified in the
data field.
In the address field, bits [31:20] have the value H'F78 indicating UTLB data array 2 and the entry
is specified by bits [13:8].
In the data field, bits [13:8] indicate EPR, and bits [7:4] indicate ESZ, respectively.
The following two kinds of operation can be applied to UTLB data array 2:
1. UTLB data array 2 read
2. UTLB data array 2 write
Rev.1.00 Jan. 10, 2008 Page 198 of 1658
REJ09B0261-0100
EPR and ESZ are read into the data field from the UTLB entry corresponding to the entry set
in the address field.
EPR and ESZ specified in the data field are written to the UTLB entry corresponding to the
entry set in the address field.
UTLB Data Array 2
Figure 7.25 Memory-Mapped UTLB Data Array 2 (TLB Extended Mode)
Address field
Data field
Legend:
E:
EPR:
ESZ:
*:
31
31
1 1 1 1 0 1 1 1 1
Entry
Protection key data
Page size bits
Don't care
0 0 0
20 19
*
* *
:
Reserved bits
(write value should be 0,
and read value is undefined)
* * *
14 13
13
EPR
E
8 7
8 7
* * * * * *
ESZ
4 3
2 1
0
0
0
0