R8A77850ANBGV Renesas Electronics America, R8A77850ANBGV Datasheet - Page 1141

• Manufacturer Part Number: R8A77850ANBGV
• Description: IC SUPERH MPU ROMLESS 436-BGA
• Manufacturer: Renesas Electronics America
• Series: SuperH® SH7780r

Specifications of R8A77850ANBGV

• Core Processor: SH-4A
• Core Size: 32-Bit
• Speed: 600MHz
• Connectivity: Audio Codec, MMC, Serial Sound, SCI, SIO, SPI, SSI
• Peripherals: DMA, POR, WDT
• Number Of I /o: 108
• Program Memory Type: ROMless
• Ram Size: 8K x 8
• Voltage - Supply (vcc/vdd): 1 V ~ 1.2 V
• Oscillator Type: External
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 436-BGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -
• Data Converters: -

22.3.4
SIRDR is a 32-bit read-only register that reads receive data of the SIOF. SIRDR stores data in the
receive FIFO.
Initial value:
Initial value:
Bit
31 to 16 SIRDL[15:0]
15 to 0
R/W:
R/W:
BIt:
BIt:
Receive Data Register (SIRDR)
Bit Name
SIRDR[15:0]
31
15
—
—
R
R
30
14
—
—
R
R
29
13
—
—
R
R
Initial
Value
Undefined
Undefined
28
—
12
—
R
R
27
—
11
—
R
R
R/W
R
R
26
10
—
—
R
R
Description
Left-Channel Receive Data
These bits store data received from the SIOF_RXD pin
as left-channel data. The position of the left-channel
data in the receive frame depends on the value set in
the RDLA bit in SIRDAR.
•
Right-Channel Receive Data
These bits store data received from the SIOF_RXD pin
as right-channel data. The position of the right-channel
data in the receive frame depends on the value set in
the RDRA bit in SIRDAR.
•
25
—
—
R
R
9
These bits are valid when the RDLE bit in SIRDAR
is set to 1.
These bits are valid when the RDRE bit in SIRDAR
is set to 1.
SIRDR[15:0]
SIRDL[15:0]
24
—
—
R
R
8
23
—
—
R
R
7
Rev.1.00 Jan. 10, 2008 Page 1109 of 1658
22
—
—
R
R
6
21
—
—
R
R
5
22. Serial I/O with FIFO (SIOF)
20
—
—
R
R
4
19
—
—
R
R
3
REJ09B0261-0100
18
—
—
R
R
2
17
—
—
R
R
1
16
—
—
R
R
0