R8A77850ANBGV Renesas Electronics America, R8A77850ANBGV Datasheet - Page 632

• Manufacturer Part Number: R8A77850ANBGV
• Description: IC SUPERH MPU ROMLESS 436-BGA
• Manufacturer: Renesas Electronics America
• Series: SuperH® SH7780r

Specifications of R8A77850ANBGV

• Core Processor: SH-4A
• Core Size: 32-Bit
• Speed: 600MHz
• Connectivity: Audio Codec, MMC, Serial Sound, SCI, SIO, SPI, SSI
• Peripherals: DMA, POR, WDT
• Number Of I /o: 108
• Program Memory Type: ROMless
• Ram Size: 8K x 8
• Voltage - Supply (vcc/vdd): 1 V ~ 1.2 V
• Oscillator Type: External
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 436-BGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -
• Data Converters: -

13. PCI Controller (PCIC)
Rev.1.00 Jan. 10, 2008 Page 600 of 1658
REJ09B0261-0100
Bit
6
5
4
Bit Name
SDI
DPEITW
PEDITR
0
0
Initial
Value
0
R/W
SH: R/WC
PCI: R
SH: R/WC
PCI: R
SH: R/WC
PCI: R
Description
SERR Detection Interrupt
Indicates that the assertion of SERR was detected
when the PCIC is a host.
0: A SERR detection interrupt was not generated
1: A SERR detection interrupt was generated
When TTADI bit is write to 0, target target-abort
interrupt is cleared. When write to 1, it is not
available.
Data Parity Error Interrupt in Target Write
Indicates that a data parity error was detected in
reception of a target write transfer when the PCIC is
a target.
Note: A data parity error in target write is detected
0: A data parity error interrupt was not generated in
1: A data parity error interrupt was generated in
When TTADI bit is write to 0, target target-abort
interrupt is cleared. When write to 1, it is not
available.
PERR Detection Interrupt in Target Read
Indicates that PERR was received in reception of a
target read transfer when the PCIC is a target.
Note: PERR is detected in target read only when bit
0: A PERR detection interrupt was not generated in
1: A PERR detection interrupt was generated in
When TTADI bit is write to 0, target target-abort
interrupt is cleared. When write to 1, it is not
available.
target write
target write
target read
target read
only when bit 6 (PER) in PCICMD is set to 1.
6 (PER) in PCICMD is set to 1.