R8A77850ANBGV Renesas Electronics America, R8A77850ANBGV Datasheet - Page 721

• Manufacturer Part Number: R8A77850ANBGV
• Description: IC SUPERH MPU ROMLESS 436-BGA
• Manufacturer: Renesas Electronics America
• Series: SuperH® SH7780r

Specifications of R8A77850ANBGV

• Core Processor: SH-4A
• Core Size: 32-Bit
• Speed: 600MHz
• Connectivity: Audio Codec, MMC, Serial Sound, SCI, SIO, SPI, SSI
• Peripherals: DMA, POR, WDT
• Number Of I /o: 108
• Program Memory Type: ROMless
• Ram Size: 8K x 8
• Voltage - Supply (vcc/vdd): 1 V ~ 1.2 V
• Oscillator Type: External
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 436-BGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -
• Data Converters: -

14.3.8
DMAOR are 16-bit readable/writable registers that specify the priority of channels in DMA
transfer. Also, these registers show the DMA transfer status.
DMAOR 0 is a register common to channels 0 to 5, and DMAOR1 is a register common to
channels 6 to11.
Initial value:
Bit
15, 14
13, 12
R/W:
Note: * To clear the flag, 0 can be written to.
Bit:
DMA Operation Register 0, 1 (DMAOR0 and DMAOR1)
Bit Name
⎯
CMS[1:0]
15
R
0
14
R
0
R/W
13
Initial
Value
All 0
00
CMS[1:0]
0
R/W
12
0
R/W
R
R/W
11
R
0
10
R
0
Descriptions
Reserved
These bits are always read as 0. The write value should
always be 0.
Cycle Steal Mode Select 1, 0
Select normal mode or intermittent mode in cycle steal
mode.
To validate intermittent mode, bus mode in all channels
(channels 0 to 5) corresponding to DMAOR0 or all
channels (channels 6 to 11) corresponding to DMAOR1
should be in cycle steal mode.
00: Normal mode
01: Setting prohibited
10: Intermittent mode 16
11: Intermittent mode 64
For details, see the descriptions on intermittent mode
16 and Intermittent mode 64, under section 14.4.3 (2)
(a), Cycle Steal Mode.
R/W
9
0
PR[1:0]
Executes a DMA transfer after waiting 16 Bck clock
of the external clock
Executes a DMA transfer after waiting 64 Bck clock
of the external clock
R/W
8
0
R
7
0
14. Direct Memory Access Controller (DMAC)
Rev.1.00 Jan. 10, 2008 Page 689 of 1658
R
6
0
R
5
0
R
4
0
R
3
0
R/(W)*R/(W)* R/W
REJ09B0261-0100
AE
2
0
NMIF DME
1
0
0
0