R8A77850ANBGV Renesas Electronics America, R8A77850ANBGV Datasheet - Page 1519
R8A77850ANBGV
Manufacturer Part Number
R8A77850ANBGV
Description
IC SUPERH MPU ROMLESS 436-BGA
Manufacturer
Renesas Electronics America
Series
SuperH® SH7780r
Datasheet
1.R8A77850AADBGV.pdf
(1694 pages)
Specifications of R8A77850ANBGV
Core Processor
SH-4A
Core Size
32-Bit
Speed
600MHz
Connectivity
Audio Codec, MMC, Serial Sound, SCI, SIO, SPI, SSI
Peripherals
DMA, POR, WDT
Number Of I /o
108
Program Memory Type
ROMless
Ram Size
8K x 8
Voltage - Supply (vcc/vdd)
1 V ~ 1.2 V
Oscillator Type
External
Operating Temperature
-20°C ~ 75°C
Package / Case
436-BGA
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Program Memory Size
-
Data Converters
-
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
R8A77850ANBGV
Manufacturer:
Renesas Electronics America
Quantity:
10 000
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30. User Debugging Interface (H-UDI)
Section 30 User Debugging Interface (H-UDI)
The H-UDI is a serial input/output interface which supports to a subset of JTAG (IEEE 1149.1).
The H-UDI is used to connect emulators.
30.1
Features
The H-UDI is a serial input/output interface which supports to a subset of JTAG (IEEE 1149.1:
IEEE Standard Test Access Port and Boundary-Scan Architecture). The H-UDI is used to connect
emulators. Do not use the JTAG functions of this interface when using an emulator. For the
method of connecting the emulator, see emulator manuals.
The H-UDI has six pins, the TCK, TMS, TDI, TDO, TRST, and ASEBRK/BRKACK pins. The
pin functions except ASEBRK/BRKACK, and serial transfer protocols conform to JTAG with the
subset. Also, the H-UDI has six signals (AUDSYNC, AUDCK, and AUDATA3 to AUDATA0)
used for emulator pins, and a signal (MPMD) for the chip mode select pin.
In the H-UDI in this LSI, the boundary-scan test access port (TAP) controller is separated from the
TAP controller for other H-UDI function control. When the TRST is asserted (including when the
power is turned on), the boundary-scan TAP controller is selected. Therefore, the switching
command should be input to use the H-UDI functions. The boundary-scan TAP controller cannot
be accessed through the CPU.
Figure 30.1 shows a block diagram of the H-UDI.
The H-UDI circuit has TAP controllers and four registers (SDBPR, SDBSR, SDIR, and SDINT).
SDBPR supports the JTAG bypass mode, SDBSR supports the JTAG boundary scan mode, SDIR
is used for commands, and SDINT is used for H-UDI interrupts. SDIR can be directly accessed
through the TDI and TDO pins.
Without reset pins of the chip, the TAP controller, control registers, and boundary-scan TAP
controller are reset when the TRST pin is set to low or when five or more TCK cycles are elapsed
after TMS is set to 1. The other circuits are reset in a normal reset period, and initialized.
Rev.1.00 Jan. 10, 2008 Page 1487 of 1658
REJ09B0261-0100
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