R8A77850ANBGV Renesas Electronics America, R8A77850ANBGV Datasheet - Page 1305

• Manufacturer Part Number: R8A77850ANBGV
• Description: IC SUPERH MPU ROMLESS 436-BGA
• Manufacturer: Renesas Electronics America
• Series: SuperH® SH7780r

Specifications of R8A77850ANBGV

• Core Processor: SH-4A
• Core Size: 32-Bit
• Speed: 600MHz
• Connectivity: Audio Codec, MMC, Serial Sound, SCI, SIO, SPI, SSI
• Peripherals: DMA, POR, WDT
• Number Of I /o: 108
• Program Memory Type: ROMless
• Ram Size: 8K x 8
• Voltage - Supply (vcc/vdd): 1 V ~ 1.2 V
• Oscillator Type: External
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 436-BGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -
• Data Converters: -

25.3.3
HACCSDR is a 32-bit read/write data register used for accessing the codec register. Write the
command data to HACCSDR and set the ST bit in the HACCR register to 1. The HAC then
transmits the data to the codec via slot 2.
After the codec has responded to a read request (HACRSR.STDRY = 1), the status data received
via slot 2 can be read out from HACCSDR. In both read and write, HACCSAR stores the related
codec register address.
Initial value:
Initial value:
R/W:
R/W:
Bit:
Bit:
Command/Status Data Register (HACCSDR)
CD11/
SD11
R/W
31
15
⎯
R
0
0
CD10/
SD10
R/W
⎯
30
14
R
0
0
CD9/
SD9
R/W
29
⎯
13
R
0
0
CD8/
SD8
R/W
28
12
⎯
R
0
0
CD7/
SD7
R/W
27
11
⎯
R
0
0
CD6/
SD6
R/W
26
⎯
10
R
0
0
CD5/
SD5
R/W
⎯
25
R
0
9
0
CD4/
SD4
R/W
24
⎯
R
0
8
0
CD3/
SD3
R/W
23
⎯
R
0
7
0
Rev.1.00 Jan. 10, 2008 Page 1273 of 1658
CD2/
SD2
R/W
22
⎯
R
0
0
6
CD1/
SD1
R/W
21
⎯
R
0
0
5
25. Audio Codec Interface (HAC)
CD0/
SD0
R/W
20
⎯
R
0
4
0
CD15/
SD15
R/W
19
⎯
R
0
3
0
REJ09B0261-0100
CD14/
SD14
R/W
18
⎯
R
0
2
0
CD13/
SD13
R/W
17
⎯
R
0
1
0
CD12/
SD12
R/W
16
⎯
R
0
0
0