R8A77850ANBGV Renesas Electronics America, R8A77850ANBGV Datasheet - Page 960

• Manufacturer Part Number: R8A77850ANBGV
• Description: IC SUPERH MPU ROMLESS 436-BGA
• Manufacturer: Renesas Electronics America
• Series: SuperH® SH7780r

Specifications of R8A77850ANBGV

• Core Processor: SH-4A
• Core Size: 32-Bit
• Speed: 600MHz
• Connectivity: Audio Codec, MMC, Serial Sound, SCI, SIO, SPI, SSI
• Peripherals: DMA, POR, WDT
• Number Of I /o: 108
• Program Memory Type: ROMless
• Ram Size: 8K x 8
• Voltage - Supply (vcc/vdd): 1 V ~ 1.2 V
• Oscillator Type: External
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 436-BGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -
• Data Converters: -

19. Display Unit (DU)
Rev.1.00 Jan. 10, 2008 Page 928 of 1658
REJ09B0261-0100
Bit
6 to 4
3
Bit Name
⎯
DISPA
Initial
Value
0
0
R/W
R/W
R
Internal
Update
None
⎯
Description
DISP Output Timing Adjustment
000: Adjustment of output timing is not
001: The DISP signal is output at the rising
010: The DISP signal is output at the rising
011: The DISP signal is output at the rising
100: The DISP signal is output at the falling
101: The DISP signal is output at the falling
110: The DISP signal is output at the falling
111: The DISP signal is output at the falling
Reserved
This bit is always read as 0. The write value
should always be 0.
performed.
The DISP signal is output at the rising edge
of the dot clock, with the reference timing.
edge, delayed one dot clock cycle relative
to the reference timing.
edge, delayed two dot clock cycles relative
to the reference timing.
edge, delayed three dot clock cycles
relative to the reference timing.
edge, preceding the reference timing by 1/2
dot clock cycle.
edge, delayed 1/2 dot clock cycle relative
to the reference timing.
edge, delayed (1+1/2) dot clock cycles
relative to the reference timing.
edge, delayed (2+1/2) dot clock cycles
relative to the reference timing.