R8A77850ANBGV Renesas Electronics America, R8A77850ANBGV Datasheet - Page 616

• Manufacturer Part Number: R8A77850ANBGV
• Description: IC SUPERH MPU ROMLESS 436-BGA
• Manufacturer: Renesas Electronics America
• Series: SuperH® SH7780r

Specifications of R8A77850ANBGV

• Core Processor: SH-4A
• Core Size: 32-Bit
• Speed: 600MHz
• Connectivity: Audio Codec, MMC, Serial Sound, SCI, SIO, SPI, SSI
• Peripherals: DMA, POR, WDT
• Number Of I /o: 108
• Program Memory Type: ROMless
• Ram Size: 8K x 8
• Voltage - Supply (vcc/vdd): 1 V ~ 1.2 V
• Oscillator Type: External
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 436-BGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -
• Data Converters: -

13. PCI Controller (PCIC)
(25) PCI Power Management Register (PCIPMC)
PCIPMC is a 16-bit register that provides information on the functions related to power
management. For details, see section 3, PCI Power Management Interface in PCI Bus Power
Management Interface Specification Revision 1.1. This register is not cleared by a power-on reset.
This register must be set during initialization of register initialization in the PCIC (CFINIT = 0 in
PCICR).
Rev.1.00 Jan. 10, 2008 Page 584 of 1658
REJ09B0261-0100
Initial value:
Bit
15 to 11 PMCS
10
9
PCI R/W:
SH R/W:
Bit:
Bit Name
D2S
D1S
15
R
R
0
14
R
R
0
PMCS
Initial
Value
00000
0
0
13
R
R
0
12
R
R
0
R/W
SH: R
PCI: R
SH: R/W
PCI: R
SH: R/W
PCI: R
11
R
R
0
D2S
R/W
10
R
0
Description
PME SUPPORT
This 5-bit field indicates the power state that asserts
PME, by using this power management function.
When these bits are 0, these bits indicate that this
function cannot assert PME at that power state (not
supported).
(Bit11) xxxx1: PME can be asserted from D0
(Bit12) xxx1x: PME can be asserted from D1
(Bit13) xx1xx: PME can be asserted from D2
(Bit14) x1xxx: PME can be asserted from D3hot
(Bit15) 1xxxx: PME can be asserted from D3cold
Note: The PCIC in this LSI dose not have the PME
D2 Support
When this bit is 1, this power management function
supports the D2 power management state. When the
D2 power management state is not supported, this bit
should always be read as 0.
D1 Support
When this bit is 1, This function supports the D1
power management state. When the D1 power
management state is not supported, this bit is read as
0.
D1S
R/W
R
9
0
pin.
⎯
R
R
8
0
⎯
R
R
7
0
⎯
R
R
6
0
DSI
R
R
5
0
⎯
R
R
4
0
PMEC
R/W
R
3
1
R/W
R
2
0
PMV
R/W
R
1
1
R/W
R
0
0