R8A77850ANBGV Renesas Electronics America, R8A77850ANBGV Datasheet - Page 700

• Manufacturer Part Number: R8A77850ANBGV
• Description: IC SUPERH MPU ROMLESS 436-BGA
• Manufacturer: Renesas Electronics America
• Series: SuperH® SH7780r

Specifications of R8A77850ANBGV

• Core Processor: SH-4A
• Core Size: 32-Bit
• Speed: 600MHz
• Connectivity: Audio Codec, MMC, Serial Sound, SCI, SIO, SPI, SSI
• Peripherals: DMA, POR, WDT
• Number Of I /o: 108
• Program Memory Type: ROMless
• Ram Size: 8K x 8
• Voltage - Supply (vcc/vdd): 1 V ~ 1.2 V
• Oscillator Type: External
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 436-BGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -
• Data Converters: -

14. Direct Memory Access Controller (DMAC)
14.3
Table 14.2 shows the register configuration.
Table 14.2 Register Configuration of the DMAC (1)
Rev.1.00 Jan. 10, 2008 Page 668 of 1658
REJ09B0261-0100
Channel Name
0
1
2
3
0 to 5
4
5
DMA source address register 0
DMA destination address register 0
DMA transfer count register 0
DMA channel control register 0
DMA source address register 1
DMA destination address register 1
DMA transfer count register 1
DMA channel control register 1
DMA source address register 2
DMA destination address register 2
DMA transfer count register 2
DMA channel control register 2
DMA source address register 3
DMA destination address register 3
DMA transfer count register 3
DMA channel control register 3
DMA operation register 0
DMA source address register 4
DMA destination address register 4
DMA transfer count register 4
DMA channel control register 4
DMA source address register 5
DMA destination address register 5
DMA transfer count register 5
DMA channel control register 5
Register Descriptions
Abbrev.
SAR0
DAR0
TCR0
CHCR0
SAR1
DAR1
TCR1
CHCR1
SAR2
DAR2
TCR2
CHCR2
SAR3
DAR3
TCR3
CHCR3
DMAOR0
SAR4
DAR4
TCR4
CHCR4
SAR5
DAR5
TCR5
CHCR5
R/W
R/W
R/W
R/W
R/W*
R/W
R/W
R/W
R/W*
R/W
R/W
R/W
R/W*
R/W
R/W
R/W
R/W*
R/W*
R/W
R/W
R/W
R/W*
R/W
R/W
R/W
R/W*
1
1
1
1
2
1
1
P4 Address
H'FC80 8020
H'FC80 8024
H'FC80 8028
H'FC80 802C
H'FC80 8030
H'FC80 8034
H'FC80 8038
H'FC80 803C
H'FC80 8040
H'FC80 8044
H'FC80 8048
H'FC80 804C
H'FC80 8050
H'FC80 8054
H'FC80 8058
H'FC80 805C
H'FC80 8060
H'FC80 8070
H'FC80 8074
H'FC80 8078
H'FC80 807C
H'FC80 8080
H'FC80 8084
H'FC80 8088
H'FC80 808C
Area 7
Address
H'1C80 8020
H'1C80 8024
H'1C80 8028
H'1C80 802C
H'1C80 8030
H'1C80 8034
H'1C80 8038
H'1C80 803C
H'1C80 8040
H'1C80 8044
H'1C80 8048
H'1C80 804C
H'1C80 8050
H'1C80 8054
H'1C80 8058
H'1C80 805C
H'1C80 8060
H'1C80 8070
H'1C80 8074
H'1C80 8078
H'1C80 807C
H'1C80 8080
H'1C80 8084
H'1C80 8088
H'1C80 808C
Access
Size*
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
16
32
32
32
32
32
32
32
32
3
Sync
clock
Bck
Bck
Bck
Bck, Pck*
Bck
Bck
Bck
Bck, Pck*
Bck
Bck
Bck
Bck, Pck*
Bck
Bck
Bck
Bck, Pck*
Bck, Pck*
Bck
Bck
Bck
Bck, Pck*
Bck
Bck
Bck
Bck, Pck*
4
4
4
4
5
4
4