R8A77850ANBGV Renesas Electronics America, R8A77850ANBGV Datasheet - Page 1376

IC SUPERH MPU ROMLESS 436-BGA

R8A77850ANBGV

Manufacturer Part Number
R8A77850ANBGV
Description
IC SUPERH MPU ROMLESS 436-BGA
Manufacturer
Renesas Electronics America
Series
SuperH® SH7780r
Datasheet

Specifications of R8A77850ANBGV

Core Processor
SH-4A
Core Size
32-Bit
Speed
600MHz
Connectivity
Audio Codec, MMC, Serial Sound, SCI, SIO, SPI, SSI
Peripherals
DMA, POR, WDT
Number Of I /o
108
Program Memory Type
ROMless
Ram Size
8K x 8
Voltage - Supply (vcc/vdd)
1 V ~ 1.2 V
Oscillator Type
External
Operating Temperature
-20°C ~ 75°C
Package / Case
436-BGA
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Program Memory Size
-
Data Converters
-

Available stocks

Company
Part Number
Manufacturer
Quantity
Price
Part Number:
R8A77850ANBGV
Manufacturer:
Renesas Electronics America
Quantity:
10 000
27. NAND Flash Memory Controller (FLCTL)
27.3.1
FLCMNCR is a 32-bit readable/writable register that specifies the type (NAND) of flash memory,
access mode, and FCE pin output.
Rev.1.00 Jan. 10, 2008 Page 1344 of 1658
REJ09B0261-0100
Initial value:
Initial value:
Bit
31 to 19
18
17
16
R/W:
R/W:
Bit:
Bit:
Common Control Register (FLCMNCR)
Bit Name
SNAND
QTSEL
R/W
FCK
SEL
31
15
R
0
0
30
14
R
R
0
0
29
13
R
R
Initial
Value
All 0
0
0
0
0
0
28
12
R
R
0
0
R/W
27
11
R/W
R
R/W
R/W
R
R
0
0
ACM[1:0]
R/W
26
10
R
0
0
Description
Reserved
These bits are always read as 0. The write value should
always be 0.
Large Capacity NAND Flash Memory Select
This bit is used to specify the NAND flash memory that
a page consists of 2048 + 64 bytes.
0: Selects the flash memory that a page consists of 512
1: Selects the flash memory that a page consists of
Quarter Flash Clock Select
0: Uses the FCLK selected by the FCKSEL bit
1: Divides the operating clock of the FLCTL (a
Note: When FCKSEL = 1, setting this bit to 1 is
Reserved
This bit is always read as 0. The write value should
always be 0.
NAND
R/W
25
WF
R
+ 16 bytes
2048 + 64 bytes
peripheral clock) by four and uses it as the FCLK
when FCKSEL = 0
0
9
0
prohibited.
24
R
R
0
8
0
23
R
R
0
7
0
22
R
R
0
6
0
21
R
R
0
5
0
20
R
R
0
4
0
R/W
CE0
19
R
0
3
0
SNAND
R/W
18
R
0
2
0
QTSEL
R/W
17
R
0
1
0
R/W
TYPE
SEL
16
R
0
0
0

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