R8A77850ANBGV Renesas Electronics America, R8A77850ANBGV Datasheet - Page 430

• Manufacturer Part Number: R8A77850ANBGV
• Description: IC SUPERH MPU ROMLESS 436-BGA
• Manufacturer: Renesas Electronics America
• Series: SuperH® SH7780r

Specifications of R8A77850ANBGV

• Core Processor: SH-4A
• Core Size: 32-Bit
• Speed: 600MHz
• Connectivity: Audio Codec, MMC, Serial Sound, SCI, SIO, SPI, SSI
• Peripherals: DMA, POR, WDT
• Number Of I /o: 108
• Program Memory Type: ROMless
• Ram Size: 8K x 8
• Voltage - Supply (vcc/vdd): 1 V ~ 1.2 V
• Oscillator Type: External
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 436-BGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -
• Data Converters: -

11. Local Bus State Controller (LBSC)
11.5.2
(1)
Area 0 is an area where bits 28 to 26 in the local bus address are 000.
The interface that can be set for this area is the SRAM, burst ROM or MPX interface.
A bus width of 8, 16, 32, or 64 bits is selectable by external pins MODE6 and MODE5 at a power-
on reset. For details, see section 11.3.2, Memory Bus Width.
When area 0 is accessed, the CS0 signal is asserted. In addition, the RD signal, which can be used
as OE, and write control signals WE0 to WE7 are asserted.
For the number of bus cycles, 0 to 25 wait cycles to be inserted can be selected with CS0WCR.
When the burst ROM interface is used, the number of a burst pitch is selectable in the range from
0 to 7 with the BW bits in CS0BCR.
Any number of wait cycles can be inserted in each bus cycle through the external wait pin (RDY).
(when the number of inserted cycles is set to 0, the RDY signal is ignored.)
When the burst ROM interface is used, the number of transfer cycles for a burst cycle is selected
in the range from 2 to 9 according to the number of wait cycles.
The setup/hold cycle of the address, the assert delay cycle of the read/write strobe signals for CS0
assertion and the CS0 negate delay cycle for the read/write strobe signals negation can be set in
the range from 0 to 7 cycles by CS0WCR. The BS hold cycles can be set to 1 or 2 when the RDS
bits in CS0WCR are not 000 in reading and the WTS bits in CS0WCR are not 000 in writing.
(2)
Area 1 is an area where bits 28 to 26 in the local bus address are 001.
The interface that can be set for this area is the SRAM, burst ROM, MPX and byte-control SRAM
interface.
The bus width can be selected from 8, 16, 32 and 64 bits by bits SZ in CS1BCR. When the MPX
interface is used, the bus width should be set to 32 or 64 bits with bits SZ in CS1BCR. When the
byte control SRAM interface is used, the bus width should be set to 16 or 32 bits.
When area 1 is accessed, the CS1 signal is asserted. The RD signal, that can be used as OE, and
write control signals WE0 to WE7 are also asserted.
Rev.1.00 Jan. 10, 2008 Page 398 of 1658
REJ09B0261-0100
Area 0
Area 1
Areas