R8A77850ANBGV Renesas Electronics America, R8A77850ANBGV Datasheet - Page 633

• Manufacturer Part Number: R8A77850ANBGV
• Description: IC SUPERH MPU ROMLESS 436-BGA
• Manufacturer: Renesas Electronics America
• Series: SuperH® SH7780r

Specifications of R8A77850ANBGV

• Core Processor: SH-4A
• Core Size: 32-Bit
• Speed: 600MHz
• Connectivity: Audio Codec, MMC, Serial Sound, SCI, SIO, SPI, SSI
• Peripherals: DMA, POR, WDT
• Number Of I /o: 108
• Program Memory Type: ROMless
• Ram Size: 8K x 8
• Voltage - Supply (vcc/vdd): 1 V ~ 1.2 V
• Oscillator Type: External
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 436-BGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -
• Data Converters: -

Bit
3
2
1
Bit Name
TADIM
MADIM
MWPDI
Initial
Value
0
0
0
R/W
SH: R/WC
PCI: R
SH: R/WC
PCI: R
SH: R/WC
PCI: R
Description
Target Abort Detection Interrupt for Master
Indicates that transaction was terminated by a target
abort when the PCIC is a master.
0: A target abort interrupt was not generated when
1: A target abort interrupt was generated when the
When TTADI bit is write to 0, target target-abort
interrupt is cleared. When write to 1, it is not
available.
Master-Abort Interrupt for Master
Indicates that transaction was terminated by a
master abort when the PCIC is a master
0: A master abort interrupt was not generated when
1: A master abort interrupt was generated when the
When TTADI bit is write to 0, target target-abort
interrupt is cleared. When write to 1, it is not
available.
Master Write PERR Detection Interrupt
Indicates that the PCIC received PERR from a target
during data write to the target and the PCIC is a
master.
Note: Master write PERR is detected only when bit 6
0: A master write PERR detection interrupt was not
1: A master write PERR detection interrupt was
When TTADI bit is write to 0, target target-abort
interrupt is cleared. When write to 1, it is not
available.
the PCIC is a master
generated
generated
PCIC is a master
the PCIC is a master
PCIC is a master
(PER) in PCICMD is set to 1.
Rev.1.00 Jan. 10, 2008 Page 601 of 1658
13. PCI Controller (PCIC)
REJ09B0261-0100