R8A77850ANBGV Renesas Electronics America, R8A77850ANBGV Datasheet - Page 601

• Manufacturer Part Number: R8A77850ANBGV
• Description: IC SUPERH MPU ROMLESS 436-BGA
• Manufacturer: Renesas Electronics America
• Series: SuperH® SH7780r

Specifications of R8A77850ANBGV

• Core Processor: SH-4A
• Core Size: 32-Bit
• Speed: 600MHz
• Connectivity: Audio Codec, MMC, Serial Sound, SCI, SIO, SPI, SSI
• Peripherals: DMA, POR, WDT
• Number Of I /o: 108
• Program Memory Type: ROMless
• Ram Size: 8K x 8
• Voltage - Supply (vcc/vdd): 1 V ~ 1.2 V
• Oscillator Type: External
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 436-BGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -
• Data Converters: -

(6)
This field is the programming interface for the class code of the IDE controller. For details of the
code value, see appendix D in PCI Local Bus Specification Revision 2.2.
Bit
7
6 to 4
3
2
1
PCI Program Interface Register (PCIPIF)
Bit Name
MIDED
⎯
PIS
OMS
PIP
Initial value:
Initial
Value
0
All 0
0
0
0
PCI R/W:
SH R/W:
Bit:
R/W
PCI: R
SH: R
PCI: R
SH: R/W
PCI: R
SH: R/W
PCI: R
SH: R/W
PCI: R
SH: R/W
MIDED
R/W
R
7
0
—
R
R
6
0
Description
PCI Master IDE Device
Specifies the PCI master IDE device.
0: PCI slave IDE device
1: PCI master IDE device
If this bit is written during register initialization
(PCICR.CFINT = 0) in the PCIC, the value of this bit is
updated. The value is not updated after initialization
(PCICR.CFINT = 1).
Reserved
These bits are always read as 0. The write value
should always be 0.
PCI Programmable Indicator (Secondary)
If this bit is written during register initialization
(PCICR.CFINT = 0) in the PCIC, the value of this bit is
updated. The value is not updated after initialization
(PCICR.CFINT = 1).
PCI Operating Mode (Secondary)
If this bit is written during register initialization
(PCICR.CFINT = 0) in the PCIC, the value of this bit is
updated. The value is not updated after initialization
(PCICR.CFINT = 1).
PCI Programmable Indicator (Primary)
If this bit is written during register initialization
(PCICR.CFINT = 0) in the PCIC, the value of this bit is
updated. The value is not updated after initialization
(PCICR.CFINT = 1).
—
R
R
5
0
—
R
R
4
0
R/W
PIS
R
3
0
OMS
Rev.1.00 Jan. 10, 2008 Page 569 of 1658
R/W
R
2
0
R/W
PIP
R
1
0
OMP
R/W
R
0
0
13. PCI Controller (PCIC)
REJ09B0261-0100