R8A77850ANBGV Renesas Electronics America, R8A77850ANBGV Datasheet - Page 894

• Manufacturer Part Number: R8A77850ANBGV
• Description: IC SUPERH MPU ROMLESS 436-BGA
• Manufacturer: Renesas Electronics America
• Series: SuperH® SH7780r

Specifications of R8A77850ANBGV

• Core Processor: SH-4A
• Core Size: 32-Bit
• Speed: 600MHz
• Connectivity: Audio Codec, MMC, Serial Sound, SCI, SIO, SPI, SSI
• Peripherals: DMA, POR, WDT
• Number Of I /o: 108
• Program Memory Type: ROMless
• Ram Size: 8K x 8
• Voltage - Supply (vcc/vdd): 1 V ~ 1.2 V
• Oscillator Type: External
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 436-BGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -
• Data Converters: -

19. Display Unit (DU)
19.3.8
The display unit extensional function enable register (DEFR) enables extension functions.
DEFR should be set during display reset (the DRES bit and DEN bit in DSYSR should be set to 1
and to 0 respectively) for external updates. If update is performed during display, the display may
flicker.
Internal update:
Internal update:
Rev.1.00 Jan. 10, 2008 Page 862 of 1658
REJ09B0261-0100
Bit
31 to 6
5
Initial value:
Initial value:
R/W:
R/W:
Bit:
Bit:
Display Unit Extensional Function Enable Register (DEFR)
Bit Name
⎯
DCKE
31
15
—
—
R
R
0
0
30
—
14
—
R
R
0
0
Initial
Value
All 0
0
29
13
—
—
R
R
0
0
28
12
—
—
R
R
0
0
R/W
R
R/W
27
11
—
—
R
R
0
0
Internal
Update
⎯
None
26
10
—
—
R
R
0
0
25
—
—
R
R
0
9
0
Description
Reserved
These bits are always read as undefined. The
write value should always be 0.
Input Dot Clock Select Enable
0: The DCLKSEL bit and bit 4 of the FRQSEL
1: The DCLKSEL bit and bit 4 of the FRQSEL
•
•
24
—
—
R
R
0
8
0
bits in the external sync control register
(ESCR) are disabled.
bits in ESCR are enabled.
The following functions can be used.
The clock from the DCLKIN pin and the DU
clock (DUck) can be selected as the input
dot clock. Selection is performed using the
DCLKSEL bit in ESCR.
The dot clock frequency division ratio can be
selected in the range 0 to 32. The frequency
division ratio is set using the FRQSEL bits in
ESCR.
23
—
—
R
R
0
7
0
22
—
—
R
R
0
6
0
DCKE
R/W
21
—
R
0
5
0
ABRE
R/W
20
—
R
0
4
0
19
—
—
R
R
0
3
0
18
—
—
R
R
0
2
0
17
—
—
R
R
0
1
0
DSAE
R/W
16
—
R
0
0
0