R8A77850ANBGV Renesas Electronics America, R8A77850ANBGV Datasheet - Page 631

• Manufacturer Part Number: R8A77850ANBGV
• Description: IC SUPERH MPU ROMLESS 436-BGA
• Manufacturer: Renesas Electronics America
• Series: SuperH® SH7780r

Specifications of R8A77850ANBGV

• Core Processor: SH-4A
• Core Size: 32-Bit
• Speed: 600MHz
• Connectivity: Audio Codec, MMC, Serial Sound, SCI, SIO, SPI, SSI
• Peripherals: DMA, POR, WDT
• Number Of I /o: 108
• Program Memory Type: ROMless
• Ram Size: 8K x 8
• Voltage - Supply (vcc/vdd): 1 V ~ 1.2 V
• Oscillator Type: External
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 436-BGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -
• Data Converters: -

Bit
9
8
7
Bit Name
TMTOI
MDEI
APEDI
Initial
Value
0
0
0
R/W
SH: R/WC
PCI: R
SH: R/WC
PCI: R
SH: R/WC
PCI: R
Description
Target Memory Read Retry Timeout Interrupt
Indicates that the master did not perform retry
processing within 2
PCIC is a target. This bit is detected only for memory
read transfers.
0: A target memory read retry timeout interrupt was
1: A target memory read retry timeout interrupt was
When TTADI bit is write to 0, target target-abort
interrupt is cleared. When write to 1, it is not
available.
Master Function Disable Error Interrupt
Indicates that the PCIC attempted to operate as a
master (PIO or DMA transfer) although bit 2 (BM) in
PCICMD is cleared to 0 and operation as a bus
master is disabled.
0: A master function disable error interrupt was not
1: A master function disable error interrupt was
When TTADI bit is write to 0, target target-abort
interrupt is cleared. When write to 1, it is not
available.
Address Parity Error Detection Interrupt
Indicates that an address parity error was detected.
Note: An address parity error is detected only when
0: An address parity error interrupt was not
1: An address parity error interrupt was generated
When TTADI bit is write to 0, target target-abort
interrupt is cleared. When write to 1, it is not
available.
generated
not generated
generated
generated
generated
both of the bits 8 (SERRE) and 6 (PER) in
PCICMD are set to 1.
Rev.1.00 Jan. 10, 2008 Page 599 of 1658
15
clocks in PCICLK when the
13. PCI Controller (PCIC)
REJ09B0261-0100