R8A77850ANBGV Renesas Electronics America, R8A77850ANBGV Datasheet - Page 228

• Manufacturer Part Number: R8A77850ANBGV
• Description: IC SUPERH MPU ROMLESS 436-BGA
• Manufacturer: Renesas Electronics America
• Series: SuperH® SH7780r

Specifications of R8A77850ANBGV

• Core Processor: SH-4A
• Core Size: 32-Bit
• Speed: 600MHz
• Connectivity: Audio Codec, MMC, Serial Sound, SCI, SIO, SPI, SSI
• Peripherals: DMA, POR, WDT
• Number Of I /o: 108
• Program Memory Type: ROMless
• Ram Size: 8K x 8
• Voltage - Supply (vcc/vdd): 1 V ~ 1.2 V
• Oscillator Type: External
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 436-BGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -
• Data Converters: -

7. Memory Management Unit (MMU)
7.7.5
The UTLB data array is allocated to addresses H'F700 0000 to H'F70F FFFF in the P4 area. A
data array access requires a 32-bit address field specification (when reading or writing) and a 32-
bit data field specification (when writing). Information for selecting the entry to be accessed is
specified in the address field, and PPN, V, SZ, PR, C, D, SH, and WT to be written to data array
are specified in the data field.
In the address field, bits [31:20] have the value H'F70 indicating UTLB data array and the entry is
specified by bits [13:8].
In the data field, bits [28:10] indicate PPN, bit [8] indicates V, bits [7] and [4] indicate SZ, bits
[6:5] indicate PR, bit [3] indicates C, bit [2] indicates D, bit [1] indicates SH, and bit [0] indicates
WT.
The following two kinds of operation can be used on UTLB data array:
1. UTLB data array read
2. UTLB data array write
Rev.1.00 Jan. 10, 2008 Page 196 of 1658
REJ09B0261-0100
PPN, V, SZ, PR, C, D, SH, and WT are read into the data field from the UTLB entry
corresponding to the entry set in the address field.
PPN, V, SZ, PR, C, D, SH, and WT specified in the data field are written to the UTLB entry
corresponding to the entry set in the address field.
UTLB Data Array (TLB Compatible Mode)
Address field
Data field
Figure 7.22 Memory-Mapped UTLB Address Array
31
31
1 1 1 1 0 1 1 0 0 0 0 0
VPN:
D:
V:
E:
*:
Virtual page number
Validity bit
Entry
Dirty bit
Don't care
20
VPN
19
* * * * *
ASID:
A:
:
Address space identifier
Association bit
Reserved bits (write value should be 0
and read value is undefined )
14 13
*
E
10 9 8 7
D
V
8 7
A
* * * * *
ASID
2 1
0 0
0
0