R8A77850ANBGV Renesas Electronics America, R8A77850ANBGV Datasheet - Page 746

• Manufacturer Part Number: R8A77850ANBGV
• Description: IC SUPERH MPU ROMLESS 436-BGA
• Manufacturer: Renesas Electronics America
• Series: SuperH® SH7780r

Specifications of R8A77850ANBGV

• Core Processor: SH-4A
• Core Size: 32-Bit
• Speed: 600MHz
• Connectivity: Audio Codec, MMC, Serial Sound, SCI, SIO, SPI, SSI
• Peripherals: DMA, POR, WDT
• Number Of I /o: 108
• Program Memory Type: ROMless
• Ram Size: 8K x 8
• Voltage - Supply (vcc/vdd): 1 V ~ 1.2 V
• Oscillator Type: External
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 436-BGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -
• Data Converters: -

14. Direct Memory Access Controller (DMAC)
• Intermittent mode 16 (DMAOR. CMS = 10, CHCR.LCKN = 0 or 1, CHCR.TB = 0)
• Intermittent mode 64 (DMAOR. CMS = 11, CHCR.LCKN = 0 or 1, CHCR.TB = 0)
(b) Burst Mode (CHCR.LCKN = 1, CHCR.TB = 1)
In burst mode, once the DMAC obtains the SuperHyway bus mastership, the transfer is performed
continuously without releasing the bus mastership until the transfer end condition is satisfied. If
the DREQ is detected at level in external request mode, when the DREQ pin is not active, the
DMAC passes bus mastership to the other bus master after the DMAC transfer request that has
already been accepted ends, even if the transfer end conditions have not been satisfied.
Burst mode is not available when an on-chip peripheral module is the transfer request source.
Burst mode can be set for only channels 0 to 5.
Figure 14.9 shows DMA transfer timing in burst mode.
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REJ09B0261-0100
SuperHyway
bus cycle
In intermittent mode of cycle steal, the DMAC gives the SuperHyway bus mastership to other
bus master whenever a one-transfer unit (byte, word, longword, or 16-byte or 32-byte unit) is
completed. After that, if the next transfer request occurs, the DMAC issues the next transfer
request after waiting for 16 or 64 clocks in Bck, transfers data of one-transfer unit again, and
returns the SuperHyway bus mastership to other bus master. These operations are repeated
until the transfer end condition is satisfied. It is possible to make lower the ratio of bus
occupation by DMA transfer than cycle steal normal modes 1 and 2.
When the DMAC issues the next transfer request again, DMA transfer can be postponed in
case of entry updating due to cache miss.
The intermittent modes must be cycle steal mode in all channels (channels 0 to 5)
corresponding to DMAOR0 or all channels (channels 6 to11) corresponding to DMAOR1.
Figure 14.8 shows an example of DMA transfer timing in cycle steal intermittent mode.
Figure 14.8 Example e of DMA Transfer Timing in Cycle Steal Intermittent Mode
DREQ
CPU
CPU
CPU
(DREQ Low Level Detection)
DMAC
Read/Write
More than 16 or 64 Bck
(depends on DMAOR.CMS settings)
DMAC
CPU
CPU
DMAC
Read/Write
DMAC
CPU