HD6417041AVF16V Renesas Electronics America, HD6417041AVF16V Datasheet - Page 112

• Manufacturer Part Number: HD6417041AVF16V
• Description: IC SUPERH MCU ROMLESS 144QFP
• Manufacturer: Renesas Electronics America
• Series: SuperH® SH7040r

Specifications of HD6417041AVF16V

• Core Processor: SH-2
• Core Size: 32-Bit
• Speed: 28.7MHz
• Connectivity: EBI/EMI, SCI
• Peripherals: DMA, POR, PWM, WDT
• Number Of I /o: 98
• Program Memory Type: ROMless
• Ram Size: 4K x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 3.6 V
• Data Converters: A/D 8x10b
• Oscillator Type: Internal
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 144-QFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -

Section 5 Instruction Set
Table 5.2
Item
Instruction
mnemonic
Instruction code
Operation
summary
Execution cycles
Instruction
execution cycles
T bit
Notes: 1. Scaled ( 1, 2, or 4) according to the size of the instruction’s operand. For more
Rev. 5.00 Jun 30, 2004 page 96 of 512
REJ09B0171-0500O
2. Instruction execution cycles: The executions cycles shown in the table are minimums.
information, see section 12, Instruction Descriptions.
The actual number of cycles may be increased when (1) contention occurs between
instruction fetches and data access, or (2) when the destination register of the load
instruction (memory
same.
Instruction Code Format
Format
OP.Sz SRC,DEST
MSB
(xx)
M/Q/T
&
|
^
~
<<n, >>n
—: No change
,
LSB
register) and the register used by the next instruction are the
Explanation
OP: Operation code
Sz: Size
SRC: Source
DEST: Destination
Rm: Source register
Rn: Destination register
imm: Immediate data
disp: Displacement*
mmmm: Source register
nnnn: Destination register
iiii: Immediate data
dddd: Displacement
Direction of transfer
Memory operand
Flag bits in the SR
Logical AND of each bit
Logical OR of each bit
Exclusive OR of each bit
Logical NOT of each bit
n-bit shift
Value when no wait states are inserted*
The execution cycles shown in the table are minimums.
The actual number of cycles may be increased:
1. When contention occurs between instruction fetches
2. When the destination register of the load instruction
Value of T bit after instruction is executed
and data access, or
(memory
next instruction are the same.
0000: R0
0001: R1
1111: R15
...........
register) and the register used by the
1
2