HD6417041AVF16V Renesas Electronics America, HD6417041AVF16V Datasheet - Page 333
HD6417041AVF16V
Manufacturer Part Number
HD6417041AVF16V
Description
IC SUPERH MCU ROMLESS 144QFP
Manufacturer
Renesas Electronics America
Series
SuperH® SH7040r
Specifications of HD6417041AVF16V
Core Processor
SH-2
Core Size
32-Bit
Speed
28.7MHz
Connectivity
EBI/EMI, SCI
Peripherals
DMA, POR, PWM, WDT
Number Of I /o
98
Program Memory Type
ROMless
Ram Size
4K x 8
Voltage - Supply (vcc/vdd)
3 V ~ 3.6 V
Data Converters
A/D 8x10b
Oscillator Type
Internal
Operating Temperature
-20°C ~ 75°C
Package / Case
144-QFP
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Program Memory Size
-
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
HD6417041AVF16V
Manufacturer:
Renesas Electronics America
Quantity:
10 000
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6.3.5
Description: Does an AND of the upper word of the Sx operand and the upper word of the Sy
operand, stores the result in the upper word of the Dz operand, and clears the bottom word of the
Dz operand with zeros. When Dz is a register that has guard bits, the guard bits are also zeroed.
When conditions are specified for DCT and DCF, the instruction is executed when those
conditions are TRUE. When they are FALSE, the instruction is not executed.
When conditions are not specified, the DC bit of the DSR register is updated according to the
specifications for the CS bits. The N, Z, V, and GT bits of the DSR register are also updated. If
conditions are specified, the DC, N, Z, V, and GT bits are not updated even is the conditions were
true and the instruction was executed.
Note: The bottom word of the destination register and the guard bits are ignored when the DC bit
Operation:
Format
PAND
Sx,Sy,Dz
DCT PAND
Sx,Sy,Dz
DCF PAND
Sx,Sy,Dz
/* PAND Sx,Sy,Dz
{
unsigned char carry_bit, negative_bit, zero_bit, overflow_bit;
/* ALU Sources assignment */
switch (xx) {
is updated.
[if cc] PAND (Logical AND): DSP Logical Operation Instruction
case 0x0: DSP_ALU_SRC1
Abstract
Sx & Sy Dz; clear LSW
of Dz
If DC = 1, SX & SY Dz,
clear LSW of Dz; if 0,
nop
If DC = 0, SX & SY Dz,
clear LSW of Dz; if 1,
nop
break;
/* Sx Operand selection bit (xx) */
*/
Code
111110**********
10010101xxyyzzzz
111110**********
10010110xxyyzzzz
111110**********
10010111xxyyzzzz
= X0;
Rev. 5.00 Jun 30, 2004 page 317 of 512
Cycle
1
1
1
Section 6 Instruction Descriptions
DC
Bit
—
—
SH-1 SH-2
—
—
—
REJ09B0171-0500O
Instructions
Applicable
—
—
—
SH-
DSP
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