HD6417041AVF16V Renesas Electronics America, HD6417041AVF16V Datasheet - Page 167
HD6417041AVF16V
Manufacturer Part Number
HD6417041AVF16V
Description
IC SUPERH MCU ROMLESS 144QFP
Manufacturer
Renesas Electronics America
Series
SuperH® SH7040r
Specifications of HD6417041AVF16V
Core Processor
SH-2
Core Size
32-Bit
Speed
28.7MHz
Connectivity
EBI/EMI, SCI
Peripherals
DMA, POR, PWM, WDT
Number Of I /o
98
Program Memory Type
ROMless
Ram Size
4K x 8
Voltage - Supply (vcc/vdd)
3 V ~ 3.6 V
Data Converters
A/D 8x10b
Oscillator Type
Internal
Operating Temperature
-20°C ~ 75°C
Package / Case
144-QFP
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Program Memory Size
-
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
HD6417041AVF16V
Manufacturer:
Renesas Electronics America
Quantity:
10 000
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6.1.13
Description: Reads the T bit and conditionally branches. If T = 1, BT/S branches after the
following instruction executes. If T = 0, BT/S executes the next instruction. The branch
destination is an address specified by PC + displacement. However, in this case it is used for
address calculation. The PC is the address 4 bytes after this instruction. The 8-bit displacement is
sign-extended and doubled. Consequently, the relative interval from the branch destination is –256
to +254 bytes. If the displacement is too short to reach the branch destination, use BT/S with the
BRA instruction or the like.
Note: Since this is a delay branch instruction, the instruction immediately following is executed
Operation:
Format
BT/S label When T = 1,
BTS(long d)
{
long disp;
unsigned
temp=PC;
if ((d&0x80)==0) disp=(0x000000FF & (long)d);
else disp=(0xFFFFFF00 | (long)d);
if (T==1) {
}
before the branch. No interrupts and address errors are accepted between this instruction
and the next instruction. When the immediately following instruction is a branch
instruction, it is recognized as an illegal slot instruction. When branching, requires two
cycles; when not branching, one cycle.
BT/S (Branch if True with Delay Slot): Branch Instruction
PC=PC+(disp<<1);
Delay_Slot(temp+2);
Abstract
disp
When T = 0, nop
/* BTS disp */
long temp;
2 + PC
PC;
Code
10001101dddddddd 2/1
Rev. 5.00 Jun 30, 2004 page 151 of 512
Cycle T Bit SH-1 SH-2
Section 6 Instruction Descriptions
—
—
REJ09B0171-0500O
Instructions
Applicable
SH-
DSP
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